ADUC834BSZ Datasheet, PDF (70/80 Pages) Analog Devices – MicroConverter, Dual 16-Bit/24-Bit

ADuC834
TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V;
all specifications T_MIN to T_MAX, unless otherwise noted.)
Parameter
32.768 kHz External Crystal
Min
Typ
Max
Unit
Figure
CLOCK INPUT (External Clock Driven XTAL1)
t_CK
XTAL1 Period
30.52
␮s
69
t_CKL
XTAL1 Width Low
6.26
␮s
69
t_CKH
XTAL1 Width High
6.26
␮s
69
t_CKR
XTAL1 Rise Time
9
␮s
69
t_CKF
XTAL1 Fall Time
9
␮s
69
1/t_CORE
ADuC834 Core Clock Frequency⁴
0.098
12.58
MHz
t_CORE
ADuC834 Core Clock Period⁵
0.636
␮s
t_CYC
ADuC834 Machine Cycle Time⁶
0.95 7.6
122.45
␮s
NOTES
1_{AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1, and VIL max}
for a Logic 0 as shown in Figure 70.
2_{For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the}
loaded V_OH/V_OL level occurs as shown in Figure 70.
3_{CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted.}
4_{ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system.}
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5_{This number is measured at the default Core_Clk operating frequency of 1.57 MHz.}
6_{ADuC834 Machine Cycle Time is nominally defined as 12/Core_Clk.}
t_CKH
t_CKR
DV_DD – 0.5V
0.45V
t_CKL
t_CKF
t_CK
Figure 69. XTAL1 Input
0.2DV_DD + 0.9V
TEST POINTS
0.2DV_DD – 0.1V
V_LOAD – 0.1V
V_LOAD
V_LOAD + 0.1V
TIMING
REFERENCE
POINTS
Figure 70. Timing Waveform Characteristics
V_LOAD – 0.1V
V_LOAD
V_LOAD + 0.1V
–70–
REV. A