ADUC834BSZ Datasheet, PDF (16/80 Pages) Analog Devices – MicroConverter, Dual 16-Bit/24-Bit

ADuC834
COMPLETE SFR MAP
Figure 6 shows a full SFR memory map and the SFR contents
after RESET. NOT USED indicates unoccupied SFR loca-
tions. Unoccupied locations in the SFR address space are not
implemented; i.e., no register exists at this location. If an unoccu-
pied location is read, an unspecified value is returned. SFR locations
that are reserved for future use are shaded (RESERVED) and
should not be accessed by user software.
ISPI WCOL SPE SPIM CPOL CPHA SPR1
SPR0 _BITS
FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0
BITS
F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0
MDO MDE MCO
MDI
I2CM I2CRS I2CTX I2CI
BITS
EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0
BITS
E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0
RDY0 RDY1 CAL NOXREF ERR0 ERR1
DFH 0 DEH 0 DDH 0 DCH 0 DBH 0 DAH 0 D9H
0 D8H
BITS
0
CY
AC
F0
RSI
RS0
OV
FI
P
BITS
D7H 0 D6H 0 D5H 0 D4H 0 D3H 0 D2H 0 D1H 0 D0H 0
TF2
EXF2 RCLK TCLK EXEN2 TR2
CNT2 CAP2
BITS
CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0
PRE3
PRE2
PRE1 PRE0 WDIR
WDS
WDE WDWR _BITS
C7H 0 C6H 0 C5H 0 C4H 1 C3H 0 C2H 0 C1H 0 C0H 0
PADC PT2
PS
PT1
PX1
BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH
PT0
PX0
BITS
B9H 0 B8H 0
RD
WR
T1
T0
INT1
INT0
TXD
RXD
BITS
B7H 1 B6H 1 B5H 1 B4H 1 B3H 1 B2H 1 B1H 1 B0H 1
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
BITS
AFH 0 AEH 0 ADH 0 ACH 0 ABH 0 AAH 0 A9H 0 A8H 0
BITS
A7H 1 A6H 1 A5H 1 A4H 1 A3H 1 A2H 1 A1H 1 A0H 1
SM0
SM1
SM2
REN
TB8
RB8
T1
R1
BITS
9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0
T2EX
T2
BITS
97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
BITS
8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0
BITS
87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1
SPICON
DACL
DACH
DACCON
RESERVED RESERVED
RESERVED RESERVED
F8H 04H
FBH 00H FCH 00H FDH 00H
B
F0H 00H
I2CCON
E8H 00H
RESERVED RESERVED
GN0L ¹
GN0M ¹
E9H 55H EAH 55H
NOT USED
GN0H ¹
EBH 53H
RESERVED
GN1L ¹
ECH 9AH
RESERVED
GN1H ¹
EDH 59H
RESERVED
RESERVED
SPIDAT
F7H 00H
RESERVED
ACC
E0H 00H
OF0L
E1H 00H
OF0M
OF0H
E2H 00H E3H 80H
OF1L
OF1H
RESERVED RESERVED
E4H 00H E5H 80H
ADCSTAT
D8H 00H
ADC0L
D9H 00H
ADC0M
ADC0H
DAH 00H DBH 00H
ADC1L
ADC1H
PSMCON
RESERVED
DCH 00H DDH 00H
DFH DEH
PSW
D0H 00H
ADCMODE
D1H 00H
ADC0CON ADC1CON
D2H 07H D3H 00H
SF
ICON
PLLCON
RESERVED
D4H 45H D5H 00H
D7H 03H
T2CON
RCAP2L
RESERVED
RCAP2H
C8H 00H
CAH 00H CBH 00H
TL2
TH2
RESERVED RESERVED
CCH 00H CDH 00H
WDCON
C0H 10H
RESERVED
CHIPID
RESERVED RESERVED RESERVED
C2H 2؋H
EADRL
C6H 00H
EADRH
C7H 00H
IP
B8H 00H
ECON
B9H 00H
EDATA1 EDATA2
RESERVED RESERVED
BCH 00H BDH 00H
EDATA3 EDATA4
BEH 00H BFH 00H
P3
PWM0L
B0H FFH B1H 00H
PWM0H
B2H 00H
PWM1L
B3H 00H
PWM1H
SPH
RESERVED ^RESERVED
B4H 00H
B7H 00H
IE
A8H 00H
P2
IEIP2
A9H A0H
TIMECON
RESERVED
HTHSEC ²
RESERVED
SEC ²
RESERVED
MIN ²
RESERVED
HOUR ²
PWMCON
AEH 00H
INTVAL
CFG834
AFH 00H
DPCON
A0H FFH A1H 00H A2H 00H A3H 00H A4H 00H A5H 00H A6H 00H ^{A7H 00H}
SCON
98H 00H
SBUF
RESERVED RESERVED
99H 00H
T3FD
NOT USED
9DH 00H
T3CON
RESERVED
9EH 00H
P1
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
90H FFH
TCON
88H 00H
TMOD
89H 00H
TL0
TL1
8AH 00H 8BH 00H
TH0
TH1
RESERVED RESERVED
8CH 00H 8DH 00H
P0
80H FFH
SP
81H 07H
DPL
DPH
82H 00H 83H 00H
DPP
PCON
RESERVED RESERVED
84H 00H
87H 00H
NOTES
1_{CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.}
2_{THESE SFRS MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1.}
SFR MAP KEY:
THESE BITS ARE CONTAINED IN THIS BYTE.
BIT MNEMONIC
BIT BIT ADDRESS
RESET DEFAULT
BIT VALUE
IE0
IT0
89H 0 88H 0
TCON
88H 00H
MNEMONIC
RESET DEFAULT VALUE
SFR ADDRESS
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE.
Figure 6. Special Function Register Locations and Their Reset Default Values
–16–
REV. A