AD9891_15 Datasheet, PDF (7/58 Pages) Analog Devices – CCD Signal Processors with Precision Timing Generator

AD9891 PIN CONFIGURATION
A1 CORNER
INDEX AREA
1 2 3 4 5 6 7 8 9 10
A
B
C
AD9891
D
TOP
E
VIEW
F
(Not to Scale)
G
H
J
K
AD9891/AD9895
PIN FUNCTION DESCRIPTIONS¹
Pin Mnemonic Type² Description
Pin Mnemonic Type² Description
A1 VD
DO Vertical Sync Pulse
K9 VSG5
DO CCD Sensor Gate Pulse 5
(Input for Slave Mode,
J9
VSG6
DO CCD Sensor Gate Pulse 6
Output for Master Mode)
K10 VSG7
DO CCD Sensor Gate Pulse 7
B1 HD
DO Horizontal Sync Pulse
J10 VSG8
DO CCD Sensor Gate Pulse 8
(Input for Slave Mode,
H10 H1
DO CCD Horizontal Clock 1
Output for Master Mode)
H9 H2
DO CCD Horizontal Clock 2
C1 SYNC
DI External System Sync Input
G10 HVDD
P
H1–H4 Driver Supply
C2 LD/FD DO Line or Field Designator
G9 HVSS
P
H1–H4 Driver Ground
Output
F10 H3
DO CCD Horizontal Clock 3
D1 DCLK
DO Data Clock Output
F9 H4
DO CCD Horizontal Clock 4
D2 CLPOB/ DO CLPOB or PBLK Output
E10 RGVDD P
RG Driver Supply
PBLK
E9 RGVSS P
RG Driver Ground
E1
NC
Not Internally Connected
D9 RG
DO CCD Reset Gate Clock
E2
NC
Not Internally Connected
D10 CLO
DO Reference Clock Output for
F2
DO/SDO DO Data Output (LSB)
Crystal
(also Serial Data Output³)
C10 CLI
DI
Reference Clock Input
F1
D1
DO Data Output
B10 TCVDD P
Analog Supply for Timing Core
G2 D2
DO Data Output
C9 TCVSS P
Analog Ground for Timing
G1 D3
DO Data Output
Core
H2 D4
DO Data Output
A10 AVDD1 P
Analog Supply for AFE
H1 D5
DO Data Output
B9
AVSS1
P
Analog Ground for AFE
J2
D6
DO Data Output
A9 BYP1
AO Analog Circuit Bypass
J1
D7
DO Data Output
B8 BYP2
AO Analog Circuit Bypass
K2 D8
DO Data Output
A8
CCDIN AI
CCD Signal Input
K1 D9
DO Data Output (MSB)
A7 BYP3
AO Analog Circuit Bypass
K3 DRVDD P
Data Output Driver Supply
B7 AVDD2 P
Analog Supply for AFE
K4 DRVSS P
Data Output Driver Ground
B6
AVSS2
P
Analog Ground for AFE
J3
VSUB
DO CCD Substrate Bias
A6 REFB
AO Voltage Reference Bottom
J4
SUBCK DO CCD Substrate Clock
Bypass
(E-Shutter)
A5 REFT
AO Voltage Reference Top Bypass
K5 V1
DO CCD Vertical Transfer Clock 1 B5 SL
DI
3-Wire Serial Load Pulse
J5
V2
DO CCD Vertical Transfer Clock 2 A4 SDI
DI
3-Wire Serial Data Input
K6 V3
DO CCD Vertical Transfer Clock 3 B4 SCK
DI
3-Wire Serial Clock
J6
V4
DO CCD Vertical Transfer Clock 4 A3 MSHUT DO Mechanical Shutter Pulse
K7 VSG1/V5 DO CCD Sensor Gate Pulse 1
B3 STROBE DO Strobe Pulse
(also V5⁴)
B2 DVSS
P
Digital Ground
J7
VSG2/V6 DO CCD Sensor Gate Pulse 2
(also V6⁴)
A2
DVDD
P
Digital Supply for VSG,
V1–V4, HD, VD, MSHUT,
K8 VSG3/V7 DO CCD Sensor Gate Pulse 3
STROBE, and Serial Interface
(also V7⁴)
J8
VSG4/V8 DO CCD Sensor Gate Pulse 4
(also V8⁴)
NOTES
1_{See Figure 50 for circuit configuration.}
2_{AI = Analog Input, AO = Analog Output, DI = Digital Input,}
DO = Digital Output, DIO = Digital Input/Output, P = Power.
3_{In Register Readback Mode}
4_{In Frame Transfer CCD Mode}
REV. A
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