AD9891_15 Datasheet, PDF (56/58 Pages) Analog Devices – CCD Signal Processors with Precision Timing Generator

AD9891/AD9895
Content
OPRMODE
[7:0]
[1:0]
[2]
[3]
[4]
[5]
[6]
[7]
CTLMODE
[5:0]
[2:0]
[3]
[4]
[5]
Bit
Width
2’h0
2’h1
2’h2
2’h3
3’h0
3’h1
3’h2
3’h3
3’h4
3’h5
3’h6
3’h7
1’h0
1’h1
1’h0
1’h1
Table XXXI. AFE Register Breakdown
Default
Value
Register Name
Register Description
8’h0
Serial Address: 10’h0{OPRMODE[5:0]},
10’h1{OPRMODE[7:6]}
POWERDOWN[1:0] Normal Operation
Standby1 (See Standby Modes Table)
Standby2 (See Standby Modes Table)
Standby3 (See Standby Modes Table)
DISBLACK
Disable Black Loop Clamping (HIGH Active)
Test Mode
Test Mode—Should Be Set LOW
Test Mode
Test Mode—Should Be Set HIGH
Test Mode
Test Mode—Should Be Set LOW
Test Mode
Test Mode—Should Be Set LOW
Test Mode
Test Mode—Should Be Set LOW
6’h0
CTLMODE[2:0]
ENABLEPXGA
OUTPUTLAT
TRISTATEOUT
Serial Address: 10’h6{CLTMODE[5:0]}
OFF
Mosaic Separate
VD Selected/Mosaic Interlaced
Mosaic Repeat
3-Color
3-Color II
4-Color
4-Color II
Enable PxGA (HIGH Active)
Latch Output Data on Selected DOUT Edge
Leave Output Latch Transparent
ADC Outputs Are Driven
ADC Outputs Are Three-Stated
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REV. A