AD9858_15 Datasheet, PDF (7/32 Pages) Analog Devices – 1 GSPS Direct Digital Synthesizer

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9858
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
D7 1
D6 2
D5 3
D4 4
DGND 5
DGND 6
DVDD 7
DVDD 8
D3 9
D2 10
D1 11
D0 12
ADDR5 13
ADDR4 14
ADDR3 15
ADDR2/IORESET 16
ADDR1/SDO 17
ADDR0/SDIO 18
WR/SCLK 19
DVDD 20
DGND 21
RD/CS 22
DVDD 23
DVDD 24
DVDD 1235
AD9858
TOP VIEW
(Not to Scale)
75 NC
74 AGND
73 AVDD
72 DIV
71 DIV
70 AVDD
69 AGND
68 CPGND
67 CPVDD
66 CP
65 CP
64 CPFL
63 CPGND
62 CPVDD
61 CPISET
60 NC
59 NC
58 PFD
57 PFD
56 IF
55 IF
54 RF
53 RF
52 AGND
51 AVDD
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES
1. NC = NO CONNECT.
2. THE TQFP_EP (THERMAL SLUG) MUST BE ATTACHED TO THE GROUND PLANE OR SOME OTHER LARGE
METAL MASS FOR THERMAL TRANSFER. FAILURE TO DO SO MAY CAUSE EXCESSIVE DIE TEMPERATURE
RISE AND DAMAGE TO THE DEVICE.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic I/O
1 to 4, 9 to 12
D7 to D0 I
5, 6, 21, 28, 95, 96 DGND
7, 8, 20, 23 to 27,
93, 94
DVDD
13 to 18
ADDR5 to I
ADDR0
16
IORESET
I
Description
Parallel Port Data. The functionality of these pins is valid only when the I/O port is configured as
a parallel port.
Digitial Ground.
Digital Supply Voltage.
When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select for
accessing the on-chip registers (see the IORESET, SDO, and SDIO pins for the serial port mode).
This is valid for serial programming mode only. Active high input signal that resets the serial I/O
bus controller. It serves as a means of recovering from an unresponsive serial bus caused by
an improper programming protocol. Asserting an I/O reset does not affect the contents of
previously programmed registers, nor does it invoke their default values.
Rev. C | Page 7 of 32