AD9772_15 Datasheet, PDF (7/30 Pages) Analog Devices – 14 BIT 150 MSPS T DAC WITH 2 INTERPOLATION FILTER

AD9772
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1, 2, 19, 20
DCOM
Digital Common.
3
DB13
Most Significant Data Bit (MSB).
4–15
DB12–DB1 Data Bits 1–12.
16
DB0
Least Significant Data Bit (LSB).
17
MOD0
Invokes digital high-pass filter response (i.e., “half-wave” digital mixing mode). Active High.
18
MOD1
Invokes “zero-stuffing” mode. Active High. Note, “quarter-wave” digital mixing occurs with
MOD0 also set HIGH.
23, 24
NC
No Connect, Leave Open.
21, 22, 47, 48 DVDD
Digital Supply Voltage (+2.7 V to +3.6 V).
OBSOLETE 25
26
27, 28
29
30
31
32
33
34
35
36
PLLLOCK
RESET
DIV1, DIV0
CLK+
CLK–
CLKCOM
CLKVDD
PLLCOM
PLLVDD
LPF
SLEEP
Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is
locked to input clock. Provides 1× clock output when PLL clock multiplier is disabled. Maxi-
mum fanout is one (i.e., <10 pF).
Resets internal divider by bringing momentarily high when PLL is disabled to synchronize inter-
nal 1× clock to the input data and/or multiple AD9772 devices.
DIV1 along with DIV0 sets the PLL’s prescaler divide ratio (refer to Table III.)
Noniverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).
Inverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).
Clock Input Common.
Clock Input Supply Voltage (+2.7 V to +3.6 V).
Phase Lock Loop Common.
Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +3.6 V). To disable PLL clock multiplier,
connect PLLVDD to PLLCOM.
PLL Loop Filter Node.
Power-Down Control Input. Active High. Connect to ACOM if not used.
37, 41, 44
ACOM
Analog Common.
38
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
39
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie
REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.
40
FSADJ
Full-Scale Current Output Adjust.
42
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
43
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
45, 46
AVDD
Analog Supply Voltage (+2.7 V to +3.6 V).
PIN CONFIGURATION
REV. 0
48 47 46 45 44 43 42 41 40 39 38 37
DCOM 1
DCOM 2
(MSB) DB13 3
DB12 4
DB11 5
DB10 6
DB9 7
DB8 8
DB7 9
DB6 10
DB5 ¹¹
DB4 12
PIN 1
IDENTIFIER
AD9772
TOP VIEW
(Not to Scale)
36 SLEEP
35 LPF
34 PLLVDD
33 PLLCOM
32 CLKVDD
31 CLKCOM
30 CLK–
29 CLK+
28 DIV0
27 DIV1
26 RESET
25 PLLLOCK
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
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