AD9772_15 Datasheet, PDF (20/30 Pages) Analog Devices – 14 BIT 150 MSPS T DAC WITH 2 INTERPOLATION FILTER

AD9772
some additional signal gain. The op amp must operate from a
dual supply since its output is approximately ± 1.0 V. A high
reduced I_OUTFS since the signal current U1 will be required to
sink will be subsequently reduced.
speed amplifier, capable of preserving the differential perform-
ance of the AD9772 while meeting other system level objectives
C_OPT
(i.e., cost, power), should be selected. The op amp’s differential
gain, its gain setting resistor values and full-scale output swing
capabilities should all be considered when optimizing this circuit.
AD9772
I_OUTFS = 10mA
R_FB
200⍀
The differential circuit shown in Figure 43 provides the neces-
sary level shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
IOUTA
IOUTB
U1
V_OUT = –I_OUTFS ؋ R_FB
200⍀
AD9772 and the op amp, is also used to level-shift the differ-
ential output of the AD9772 to midsupply (i.e., AVDD/2). The
AD8057 is a suitable op amp for this application.
Figure 45. Unipolar Buffered Voltage Output
OBSOLETE AD9772
IOUTA
IOUTB
225⍀
C_OPT
225⍀
500⍀
AD8057
1k⍀
25⍀
25⍀
1k⍀
AVDD
Figure 43. Single Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 44 shows the AD9772 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50 Ω cable since the nominal full-scale current, I_OUTFS, of
20 mA flows through the equivalent R_LOAD of 25 Ω. In this case,
R_LOAD represents the equivalent load resistance seen by IOUTA.
The unused output (IOUTB) can be connected to ACOM
POWER AND GROUNDING CONSIDERATIONS
The AD9772 contains the four following power supply inputs:
AVDD, DVDD, CLKVDD and PLLVDD. The AD9772 is
specified to operate over a 2.7 V to 3.6 V supply range, thus
accommodating +3.0 V and/or 3.3 V power supplies with up to
± 10% regulation. However, the following two conditions must
be adhered to when selecting power supply sources for AVDD,
DVDD, CLKVDD, and PLLVDD:
1. PLLVDD = CLKVDD when PLL Clock Multiplier enabled.
(Otherwise PLLVDD = PLLCOM)
2. DVDD = CLKVDD ± 0.30 V
To meet the first condition, PLLVDD must be driven by the
same power source as CLKVDD with each supply input inde-
pendently decoupled with a 0.1 µF capacitor to its respective
grounds. To meet the second condition, CLKVDD can share
the power supply source as DVDD, using the decoupling net-
directly. Different values of I_OUTFS and R_LOAD can be selected as
long as the positive compliance range is adhered to. One addi-
work shown in Figure 46 to isolate digital noise from the sensi-
tive CLKVDD (and PLLVDD) supply. Alternatively, separate
tional consideration in this mode is the integral nonlinearity
precision voltage regulators can be used to ensure that condition
(INL) as discussed in the Analog Output section of this data
two is met.
sheet. For optimum INL performance, the single-ended, buff-
In systems seeking to simultaneously achieve high speed and
ered voltage output configuration is suggested.
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
AD9772
I_OUTFS = 20mA
IOUTA
V_OUTA = 0V TO +0.5V
design. Proper RF techniques must be used in device selection,
placement and routing and supply bypassing and grounding.
Figures 54–61 illustrate the recommended printed circuit board
IOUTB
50⍀
50⍀
ground, power and signal plane layouts that are implemented on
the AD9772 evaluation board.
Figure 44. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 45 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9772
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC’s INL performance as discussed in the Analog
Output section. Although this single-ended configuration typi-
cally provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates is often limited by
U1’s slewing capabilities. U1 provides a negative unipolar output
voltage and its full-scale output voltage is simply the product of
R_FB and I_OUTFS. The full-scale output should be set within U1’s
voltage output swing capabilities by scaling I_OUTFS and/or R_FB.
An improvement in ac distortion performance may result with a
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9772 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. AVDD, CLKVDD, and PLLVDD must be powered from
a clean analog supply and decoupled to their respective analog
common (i.e., ACOM, CLKCOM and PLLCOM) as close to
the chip as physically possible. Similarly, DVDD, the digital
supply, should be decoupled to DCOM.
For those applications requiring a single +3 V or +3.3 V supply
for both the analog, digital supply and Phase Lock Loop supply,
a clean AVDD and/or CLKVDD may be generated using the
circuit shown in Figure 46. The circuit consists of a differential
LC filter with separate power supply and return lines. Lower
noise can be attained using low ESR-type electrolytic and tanta-
lum capacitors.
–20–
REV. 0