AD7918_15 Datasheet, PDF (7/28 Pages) Analog Devices – 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP

Data Sheet
AD7908/AD7918/AD7928
AD7928 SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)²
Signal-to-Noise Ratio (SNR)²
Total Harmonic Distortion (THD)²
Peak Harmonic or Spurious Noise
(SFDR)²
Intermodulation Distortion (IMD)²
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation²
Full Power Bandwidth
DC ACCURACY²
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 × REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
B Version¹
70
69.5
69
70
69.5
−77
−73
−78
−76
−90
−90
10
50
−85
8.2
1.6
12
±1
−0.9/+1.5
±8
±0.5
±1.5
±0.5
Unit
dB min
dB min
dB min
dB min
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
±1.5
±0.5
±8
±0.5
±1
±0.5
0 to REFIN
0 to 2 × REFIN
±1
20
2.5
±1
36
0.7 × VDRIVE
0.3 × VDRIVE
±1
10
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
μA max
pF typ
V
μA max
kΩ typ
V min
V max
μA max
pF max
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
@ 5 V, B models
@ 5 V, W models
@ 3 V typically 70 dB
B models
W models
@ 5 V typically −84 dB
@ 3 V typically −77 dB
@ 5 V typically −86 dB
@ 3 V typically −80 dB
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Straight binary output coding
Typically ±0.5 LSB
−REFIN to +REFIN biased about REFIN with twos
complement output coding
Typically ±0.8 LSB
RANGE bit set to 1
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
±1% specified performance
fSAMPLE = 1 MSPS
Typically 10 nA, VIN = 0 V or VDRIVE
Rev. E | Page 7 of 28