ADV7188BSTZ Datasheet, PDF (68/112 Pages) Analog Devices – Multiformat SDTV Video Decoder with Fast Switch Overlay Support

ADV7188
VPS/PDC/UTC/Gemstar
The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and therefore is available
only through the ancillary stream. For evaluation purposes, any
one line of Gemstar is available through the I²C registers sharing
the same register space as PDC, UTC, and VPS. Therefore, only
one of the following standards can be read through the I²C at a
time: VPS, PDC, UTC, or Gemstar.
To identify the data that should be made available in the I²C
registers, the user must program I2C_GS_VPS_PDC_UTC [1:0]
(Address 0x9C, user sub map).
I2C_GS_VPS_PDC_UTC (VDP) [1:0], Address 0x9C [6:5],
User Sub Map
These bits specify which standard result is available for I²C
readback.
Table 82. I2C_GS_VPS_PDC_UTC [1:0] Function
I2C_GS_VPS_PDC_UTC [1:0]
Description
00 (default)
Gemstar 1×/2×
01
VPS
10
PDC
11
UTC
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
1—Reinitializes the GS/PDC/VPS/UTC data readback registers.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78 [4], User Sub Map, Read Only
0—GS, PDC, VPS, or UTC data was not detected.
1—GS, PDC, VPS, or UTC data was detected.
VDP_GS_VPS_PDC_UTC Readback Registers,
Addresses 0x84 to 0x90, User Sub Map
See Table 83.
VPS
The VPS data bits are biphase decoded by the VDP. The
decoded data is available in both the ancillary stream and in
the I²C readback registers. VPS decoded data is available in the
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Addresses 0x84 to 0x90, user sub map). The
GS_VPS_PDC_UTC_AVL bit is set if the user had programmed
I2C_GS_VPS_PDC_UTC to 01, as explained in Table 82.
Gemstar
The Gemstar decoded data is available in the ancillary stream,
and any one line of Gemstar is available in I²C registers for
evaluation purposes. To obtain the Gemstar results in the I²C
registers, the user must program I2C_GS_VPS_PDC_UTC to
00, as explained in Table 82.
VDP supports autodetection of Gemstar, distinguishing between
Gemstar 1× and Gemstar 2×, and decodes data accordingly. For
this autodetection mode to operate correctly, the user must set
the AUTO_DETECT_GS_TYPE I²C bit (Register 0x61, user
sub map) and program the decoder to decode Gemstar 2× on
the required lines through line programming. The type of
Gemstar decoding can be determined by observing the
GS_DATA_TYPE bit (Register 0x78, user sub map).
AUTO_DETECT_GS_TYPE, Address 0x61 [4],
User Sub Map
0 (default)—Disables autodetection of Gemstar type.
1—Enables autodetection of Gemstar type.
GS_DATA_TYPE, Address 0x78 [5],
User Sub Map, Read Only
This bit identifies the decoded Gemstar data type.
0—Gemstar 1× mode is detected. Read two data bytes from 0x84.
1—Gemstar 2× mode is detected. Read four data bytes from 0x84.
The Gemstar data that is available in the I²C register may be
from any line of the input video on which Gemstar was
decoded. To read the Gemstar data on a particular video line,
the user should use the manual configuration as described in
Table 67 and Table 68 and enable Gemstar decoding only on the
required line.
Rev. A | Page 68 of 112