ADUC7121 Datasheet, PDF (68/96 Pages) Analog Devices – Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU

ADuC7121
Preliminary Technical Data
Table 94. I2CxSCTL MMR Bit Designations
Bit Name
Description
15:11
Reserved bits.
10 I2CSTXENI Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
9
I2CSRXENI Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
8
I2CSSENI I²C stop condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I²C bus.
Clear this interrupt source.
7
I2CNACKEN I²C no acknowledge enable bit.
Set this bit to no acknowledge the next byte in the transmission sequence.
Clear this bit to let the hardware control the acknowledge/no acknowledge sequence.
6
I2CSSEN
I²C slave SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
5
I2CSETEN I²C early transmit interrupt enable bit.
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
4
I2CGCCLR I²C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.
Clear this bit at all other times.
3
I2CHGCEN I²C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received a
general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register.
If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention
from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The
ADuC7121 watches for these addresses. The device that requires attention embeds its own address into the
message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB
of the I2CxALT register should always be written to 1, as per the I²C January 2000 bus specification.
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
Clear to disable recognition of hardware general call commands.
2
I2CGCEN I²C general call enable. Set this bit to enable the slave device to acknowledge an I²C general call, Address 0x00
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave
address by hardware) as the data byte, the I²C interface resets as per the I²C January 2000 bus specification. This
command can be used to reset an entire I²C system. If it receives a 0x04 (write programmable part of the slave
address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must
take corrective action by reprogramming the device address.
Set this bit to allow the slave acknowledge I²C general call commands.
Clear to disable recognition of general call commands.
1
Reserved Always set this bit to 0.
0
I2CSEN
I²C slave enable bit.
Set by the user to enable I²C slave mode.
Clear to disable I²C slave mode.
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