AD9522-4 Datasheet, PDF (67/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO

AD9522-4
Table 52. PLL
Reg.
Addr
(Hex) Bit(s) Name
010 [7] PFD polarity
010 [6:4] CP current
010 [3:2] CP mode
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.
The on-chip VCO requires positive polarity, [7] = 0.
[7] = 0; positive (higher control voltage produces higher frequency) (default).
[7] = 1; negative (higher control voltage produces lower frequency).
Charge pump current (with CPRSET = 5.1 kΩ).
[6] [5] [4]
ICP (mA)
00
0
0.6
00
1
1.2
01
0
1.8
01
1
2.4
10
0
3.0
10
1
3.6
11
0
4.2
11
1
4.8 (default)
Charge pump operating mode.
[3] [2] Charge Pump Mode
00
High impedance state.
01
Force source current (pump up).
10
Force sink current (pump down).
11
Normal operation (default).
010 [1:0] PLL power-
down
PLL operating mode.
[1] [0] Mode
0 0 Normal operation; this mode must be selected to use the PLL.
0 1 Asynchronous power-down (default).
1 0 Unused.
1 1 Synchronous power-down.
011 [7:0] 14-bit R counter, Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is
Bits[7:0] (LSB) 14 bits long. The lower eight bits are in this register (default: 0x01).
012 [5:0] 14-bit R counter, Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is
Bits[13:8] (MSB) 14 bits long. The upper six bits are in this register (default: 0x00).
013 [5:0] 6-bit A counter A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).
014 [7:0] 13-bit B counter, B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).
Bits[7:0] (LSB)
015 [4:0] 13-bit B counter, B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).
Bits[12:8] (MSB)
016 [7] Set CP pin
to VCP/2
Sets the CP pin to one-half of the VCP supply voltage.
[7] = 0; CP normal operation (default).
[7] = 1; CP pin set to VCP/2.
016 [6] Reset R counter Reset R counter (R divider).
[6] = 0; normal (default).
[6] = 1; hold R counter in reset.
016 [5] Reset A and B
counters
Reset A and B counters (part of N divider).
[5] = 0; normal (default).
[5] = 1; hold A and B counters in reset.
016 [4] Reset all
counters
Reset R, A, and B counters.
[4] = 0; normal (default).
[4] = 1; hold R, A, and B counters in reset.
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