AD9557 Datasheet, PDF (66/92 Pages) Analog Devices – Dual Input Multiservice

AD9557
Data Sheet
SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108)
Table 42. System Clock PLL Feedback Divider (N3 Divider)
Address Bits Bit Name
Description
0x0100 [7:0] SYSCLK N3 divider
System clock PLL feedback divider value: 4 ≤ N3 ≤ 255 (default: 0x08).
Table 43. SYSCLK Configuration
Address Bits Bit Name
0x0101 [7:5] Reserved
4
Load from ROM (reserved)
3
SYSCLK XTAL enable
[2:1] SYSCLK P divider
0
SYSCLK doubler enable
Description
Reserved.
This reserved bit has no function.
0 (default) = power-on default and ROM not loaded.
1 = ROM values are loaded into the register space.
Enables the crystal maintaining amplifier for the system clock input.
1 (default) = crystal mode (crystal maintaining amplifier enabled).
0 = external XO or other system clock source.
System clock input divider.
00 (default) = 1.
01 = 2.
10 = 4.
11 = 8.
Enable clock doubler on system clock input to reduce noise.
0 = disable.
1 (default) = enable.
Table 44. Nominal System Clock Period
Address Bits Bit Name
0x0103 [7:0] Nominal system clock period (fs)
0x0104 [7:0]
0x0105
[7:5] Reserved
[4:0] Nominal system clock period (fs)
Description
System clock period, Bits[7:0].
Default: 0x0E.
System clock period, Bits[15:8].
Default: 0x67.
Reserved.
System clock period, Bits[20:16].
Default: 0x13.
Table 45. System Clock Stability Period
Address Bits Bit Name
0x0106 [7:0] System clock stability period (ms)
0x0107 [7:0]
0x0108
[7:5] Reserved
4
Reset SYSCLK stability timer
[3:0] System clock stability period
Description
System clock period, Bits[7:0].
Default: 0x32 (0x000032 = 50 ms).
System clock period, Bits[15:8].
Default: 0x00.
Reserved.
This autoclearing bit resets the system clock stability timer.
System clock period, Bits[19:16].
Default: 0x00.
Rev. A | Page 66 of 92