AD9557 Datasheet, PDF (34/92 Pages) Analog Devices – Dual Input Multiservice

AD9557
System Clock Stability Timer
Because the reference monitors depend on the system clock
being at a known frequency, it is important that the system
clock be stable before activating the monitors. At initial power-
up, the system clock status is not known, and, therefore, it is
reported as being unstable. After the part has been programmed,
the system clock PLL (if enabled) eventually locks.
Data Sheet
When a stable operating condition is detected, a timer is run
for the duration that is stored in the system clock stability
period registers. If, at any time during this waiting period, the
condition is violated, the timer is reset and halted until a stable
condition is reestablished. After the specified period elapses,
the AD9557 reports the system clock as stable.
Rev. A | Page 34 of 92