ADUC7128 Datasheet, PDF (65/92 Pages) Analog Devices – Precision Analog Microcontroller ARM7TDMI MCU with 12-bit ADC & DDS DAC

Preliminary Technical Data
ADuC7128
SPICON Register
Name
Address
SPICON
0xFFFF0A10
Default Value
0x0000
SPICON is a 16-bit control register.
Access
RW
Table 62. SPICON MMR Bit Descriptions
Bit
Description
15 - 13 Reserved.
12
Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data
is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPITX register, then a new transfer is initiated after a stall period.
11
Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
10
Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output.
9
Slave Select Input Enable. Set by user in master mode to enable the output.
8
SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
7
SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data.
6
Transfer and Interrupt Mode (Master Mode). Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs
when TX is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs when RX is full.
5
LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
4
Reserved.
Should be set to ‘0’
3
Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
2
Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the
serial clock pulses at the end of each serial bit transfer.
1
Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode.
0
SPI Enable Bit. Set by user to enable the SPI. Cleared to disable the SPI.
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