ADUC7128 Datasheet, PDF (64/92 Pages) Analog Devices – Precision Analog Microcontroller ARM7TDMI MCU with 12-bit ADC & DDS DAC

ADuC7128
SERIAL PERIPHERAL INTERFACE
The ADuC7128 integrates a complete hardware serial
peripheral interface (SPI) on-chip. SPI is an industry standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and simultaneously received, that is,
full duplex up to a maximum bit rate of 1.6 Mb. The SPI
interface is only operational with core clock divider bits
POWCON[2:0] = 0, 1, or 2.
The SPI port can be configured for master or slave operation
and typically consists of four pins, namely: MISO, MOSI, SCL,
and CS.
MISO (Master In, Slave Out) Data I/O Pin
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
SCL (Serial Clock) I/O Pin
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
f _serialclock
=
f _HCLK
2 × (1 + SPIDIV)
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 1.6 Mbs at CD = 0.
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
Preliminary Technical Data
Chip Select (CS) Input Pin
In
SPI
slave
mode,
a
transfer
is
initiated
by
the
assertion
of
CS
A
E
,.EA
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
desassertion
of
CS
A
E
.EA
In
slave
mode,
CS
A
E
isEA
always
an
input.
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPISTA Register
Name
Address
SPISTA
0xFFFF0A00
Default Value
0x00
SPISTA is an 8-bit read only status register.
Access
RW
Table 61. SPISTA MMR Bit Descriptions
Bit Description
7, 6 Reserved.
5
SPIRX data register overflow status bit. Set if SPIRX is
overflowing. Cleared by reading SPISRX register.
4
SPIRX data register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
3
SPIRX data register full status bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
2
SPITX data register underflow status bit. Set auto-
matically if SPITX is under flowing. Cleared by writing in
the SPITX register.
1
SPITX data register IRQ. Set automatically if bit 0 is clear
or bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
0
SPITX data register empty status bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
SPIRX Register
Name
Address
SPIRX
0xFFFF0A04
Default Value
0x00
SPIRX is an 8-bit read only receive register.
Access
R
SPITX Register
Name
Address
SPITX
0xFFFF0A08
Default Value
0x00
SPITX is an 8-bit write only transmit register.
Access
W
SPIDIV Register
Name
Address
SPIDIV
0xFFFF0A0C
Default Value
0x1B
SPIDIV is an 8-bit serial clock divider register.
Access
RW
Rev. PrA | Page 64 of 92