ADV7343_15 Datasheet, PDF (61/108 Pages) Analog Devices – Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs

Data Sheet
ADV7342/ADV7343
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD;
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not made during active video but take
effect prior to the start of the active video on the next field.
Double buffering can be activated on the following ED/HD
registers using Subaddress 0x33, Bit 7: the ED/HD Gamma A
and Gamma B curves and ED/HD CGMS registers.
Double buffering can be activated on the following SD registers
using Subaddress 0x88, Bit 2: the SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0] (Subaddress
0xE0, Bits[5:0]) registers.
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0A to Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 66.
DAC 4 to DAC 6 are controlled by Register 0x0A.
DAC 1 to DAC 3 are controlled by Register 0x0B.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV
300mV
In Case B of Figure 66, the video output signal is reduced. The
absolute level of the sync tip and the blanking level decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
The reset value of the control registers is 0x00; that is, nominal
DAC current is output. Table 51 shows how the output current
of the DACs varies for a nominal 4.33 mA output current.
Table 51. DAC Gain Control
Subaddress 0x0A
or Subaddress
DAC
0x0B
Current (mA)
0100 0000 (0x40) 4.658
0011 1111 (0x3F) 4.653
0011 1110 (0x3E) 4.648
...
...
...
...
0000 0010 (0x02) 4.43
0000 0001 (0x01) 4.38
0000 0000 (0x00) 4.33
1111 1111 (0xFF)
1111 1110 (0xFE)
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
4.25
4.23
...
...
4.018
4.013
4.008
% Gain
7.5000%
7.3820%
7.3640%
...
...
0.0360%
0.0180%
0.0000%
−0.0180%
−0.0360%
...
...
−7.3640%
−7.3820%
−7.5000%
Note
Reset value,
nominal
GAMMA CORRECTION
CASE B
700mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0A, 0x0B
Subaddress 0x44 to Subaddress 0x57 for ED/HD;
Subaddress 0xA6 to Subaddress 0xB9 for SD
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output brightness
level (as perceived on a CRT). It can also be applied wherever
nonlinear processing is used.
Gamma correction uses the function
300mV
SignalOUT = (SignalIN)^γ
where γ is the gamma correction factor.
Figure 66. Programmable DAC Gain—Positive and Negative Gain
In Case A of Figure 66, the video output signal is gained. The
absolute level of the sync tip and the blanking level increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
Gamma correction is available for SD and ED/HD video. For
both variations, there are twenty 8-bit registers. They are used
to program the Gamma Correction Curve A and Gamma
Correction Curve B.
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
Rev.D | Page 61 of 108