ADV7343_15 Datasheet, PDF (43/108 Pages) Analog Devices – Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs

Data Sheet
ADV7342/ADV7343
SR7 to
SR0
0x8B
Register
SD Timing Register 1
(applicable in master
modes only, that is,
Subaddress 0x8A, Bit
0 = 1)
Bit Description
SD HSYNC width
SD HSYNC to VSYNC delay
SD HSYNC to VSYNC rising
edge delay (Mode 1 only)
SD VSYNC width (Mode 2 only)
SD HSYNC to pixel data adjust
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
SD FSC Register 0³
Subcarrier Frequency Bits[7:0]
SD FSC Register 1³
Subcarrier Frequency Bits[15:8]
SD FSC Register 2³
SD FSC Register 3³
SD FSC Phase
SD Closed Captioning
SD Closed Captioning
Subcarrier Frequency
Bits[23:16]
Subcarrier Frequency
Bits[31:24]
Subcarrier Phase Bits[9:2]
Extended data on even fields
Extended data on even fields
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Data on odd fields
Data on odd fields
Pedestal on odd fields
Pedestal on odd fields
Pedestal on even fields
Pedestal on even fields
Bit Number¹
76543210
00
01
10
11
00
01
10
11
X² 0
X² 1
00
01
10
11
00
01
10
11
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17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
17 16 15 14 13 12 11 10
25 24 23 22 21 20 19 18
Register Setting
ta = one clock cycle.
ta = four clock cycles.
ta = 16 clock cycles.
ta = 128 clock cycles.
tb = 0 clock cycles.
tb = four clock cycles.
tb = eight clock cycles.
tb = 18 clock cycles.
tc = tb.
tc = tb + 32 µs.
One clock cycle.
Four clock cycles.
16 clock cycles.
128 clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Subcarrier Frequency
Bits[7:0]
Subcarrier Frequency
Bits[15:8].
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24].
Subcarrier Phase Bits[9:2].
Extended Data Bits[7:0].
Extended Data
Bits[15:8].
Data Bits[7:0].
Data Bits[15:8].
Setting any of these bits
to 1 disables the
pedestal on the line
number indicated by
the bit settings.
Reset
Value
0x00
0x1F
0x7C
0xF0
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
1 _{x = Logic 0 or Logic 1.}
2 _{X = don’t care.}
3 _{SD subcarrier frequency registers default to NTSC subcarrier frequency values.}
Rev.D | Page 43 of 108