AD9135 Datasheet, PDF (61/117 Pages) Analog Devices – Digital-to-Analog Converters

Data Sheet
Configuration Mismatch IRQ
The AD9135/AD9136 have a configuration mismatch flag that
is available as an IRQ event. Use Register 0x47B[3] to enable the
mismatch flag (it is enabled by default), and then use
Register 0x47B[4] to read back its status and reset the IRQ
signal. See the Interrupt Request Operation section for more
information.
The configuration mismatch event flag is high when the link
configuration settings (in Register 0x450 to Register 0x45D) do
not match the JESD204B transmitted settings (Register 0x400 to
Register 0x40D). All these registers are paged per link (in
Register 0x300). For Mode 11 through Mode 13, the
configuration mismatch flag is high because the values for the
M and L parameters sent over the link do not match the
parameters programmed to Register 0x453 and Register 0x456.
Note that this function is different from the good checksum
flags in Register 0x472. The good checksum flags ensure that
the transmitted checksum matches a calculated checksum based
on the transmitted settings. The configuration mismatch event
ensures that the transmitted settings match the configured settings.
HARDWARE CONSIDERATIONS
Power Supply Recommendations
The power supply domains are described in Table 59. The
power supplies can be grouped into separate PCB domains as
show in Figure 67. All the AD9135/AD9136 supply domains
must remain as noise free as possible for the best operation.
Power supply noise has a frequency component that affects
performance, and is specified in terms of V rms. Figure 68
shows the recommended power supply components.
An LC filter on the output of the power supply is recommended
to attenuate the noise, and must be placed as close to the
AD9135/AD9136 as possible. An effective filter is shown in
Figure 67. This filter scheme reduces high frequency noise
components. Each of the power supply pins of the AD9135/
AD9136 must also have a 0.1 μF capacitor connected to the
ground plane, as shown in Figure 67. Place the capacitor as close
to the supply pin as possible. Adjacent power pins can share a
bypass capacitor. Connect the ground pins of the AD9135/
AD9136 to the ground plane using vias.
AD9135/AD9136
Power and Ground Planes
Solid ground planes are recommended to avoid ground loops
and to provide a solid, uninterrupted ground reference for the
high speed transmission lines that require controlled impedances.
Do not use segmented power planes as a reference for controlled
impedances unless the entire length of the controlled impedance
trace traverses across only a single segmented plane. These and
additional guidelines for the topology of high speed transmission
lines are described in the JESD204B Serial Interface Inputs
(SERDIN0± to SERDIN7±) section.
Table 59. Power Supplies
Supply Domain Voltage (V)
DVDD12¹
1.2
PVDD12²
1.2
SVDD12³
1.2
CVDD12¹
1.2
IOVDD
1.8
VTT4
1.2
SIOVDD33
3.3
AVDD33
3.3
Circuitry
Digital core
DAC PLL
JESD204B receiver interface
DAC clocking
SPI interface
VTT
Sync LVDS transmit
DAC
1 _{This supply requires a 1.3 V supply when operating at maximum DAC sample}
rates. See Table 3 for details.
2 _{This supply can be combined with CVDD12 on the same regulator with a}
separate supply filter network and sufficient bypass capacitors near the pins.
3 _{This supply requires a 1.3 V supply when operating at maximum interface}
rates. See Table 4 for details.
4 _{This supply can be connected to SVDD12 and does not need separate circuitry.}
Rev. A | Page 61 of 117