AD9135 Datasheet, PDF (6/117 Pages) Analog Devices – Digital-to-Analog Converters

AD9135/AD9136
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
Low
MAXIMUM DAC UPDATE RATE¹
ADJUSTED DAC UPDATE RATE
INTERFACE⁴
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK⁵ Frequency (PLL Mode)
SYSTEM REFERENCE INPUT
(SYSREF+, SYSREF−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
SYSREF± Frequency⁶
SYSREF SIGNAL TO DAC CLOCK⁷
Setup Time
Hold Time
Keep Out Window
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
Symbol Test Conditions/Comments
1.8 V  IOVDD  3.3 V
1.8 V  IOVDD  3.3 V
1.8 V  IOVDD  3.3 V
1.8 V  IOVDD  3.3 V
1× interpolation² (see Table 4)
2× interpolation²
4× interpolation³
8× interpolation³
1× interpolation
2× interpolation
4× interpolation
8× interpolation
Per lane
Per lane, SVDD12 = 1.3 V ± 2%
Self biased input, ac-coupled
6.0 GHz ≤ fVCO ≤ 12.0 GHz
tSSD
tHSD
KOW
SCLK
tPWH
tPWL
tDS
tDH
SYSREF differential swing = 0.4 V, slew
rate = 1.3 V/ns, common modes tested:
ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V
IOVDD = 1.8 V
Min
0.7 × IOVDD
0.75 × IOVDD
2120
2120
2800
2800
2120
1060
700
350
10.64
400
2800
35
400
0
131
119
10
5
2
Typ
8
1000
600
1000
20
Max
0.3 × IOVDD
0.25 × IOVDD
1.44
2000
1000
2000
2000
fDATA/(K × S)
8
12
Unit
V
V
V
V
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
Lanes
Gbps
Gbps
mV
mV
MHz
MHz
mV
mV
Hz
ps
ps
ps
MHz
ns
ns
ns
ns
Rev. A | Page 6 of 117