AD9517-3_15 Datasheet, PDF (60/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.0 GHz VCO

AD9517-3
Data Sheet
Table 54. PLL
Reg.
Addr.
(Hex)
Bits Name
0x010 7
PFD polarity
[6:4] CP current
[3:2] CP mode
[1:0] PLL power-down
0x011
0x012
0x013
0x014
0x015
0x016
[7:0] 14-bit R divider,
Bits[7:0] (LSB)
[5:0] 14-bit R divider,
Bits[13:8] (MSB)
[5:0] 6-bit A counter
[7:0] 13-bit B counter,
Bits[7:0] (LSB)
[4:0] 13-bit B counter,
Bits[12:8] (MSB)
7
Set CP pin to VCP/2
6
Reset R counter
5
Reset A, B counters
4
Reset all counters
3
B counter
bypass
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0b.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6 5 4 ICP (mA)
0 0 0 0.6
0 0 1 1.2
0 1 0 1.8
0 1 1 2.4
1 0 0 3.0
1 0 1 3.6
1 1 0 4.2
1 1 1 4.8 (default)
Charge pump operating mode.
3 2 Charge Pump Mode
0 0 High impedance state.
0 1 Force source current (pump up).
1 0 Force sink current (pump down).
1 1 Normal operation (default).
PLL operating mode.
1 0 Mode
0 0 Normal operation.
0 1 Asynchronous power-down (default).
1 0 Normal operation.
1 1 Synchronous power-down.
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Sets the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
Resets R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
Resets A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
Resets R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
Rev. E | Page 60 of 80