AD9517-3_15 Datasheet, PDF (14/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.0 GHz VCO

AD9517-3
PD, SYNC, AND RESET PINS
Table 15.
Parameter
INPUT CHARACTERISTICS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
LD, STATUS, AND REFMON PINS
Table 16.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage High (VOH)
Output Voltage Low (VOL)
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range (REF1 and REF2 Only)
LD PIN COMPARATOR
Trip Point
Hysteresis
Data Sheet
Min Typ Max Unit
2.0
V
0.8 V
1 µA
110
µA
2
pF
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up
resistor
50
ns
1.5
High speed High speed clock is CLK input signal
clock cycles
Min Typ Max Unit
2.7
V
0.4 V
100
MHz
3
pF
1.02
MHz
8
kHz
1.6
V
260
mV
Test Conditions/Comments
When selected as a digital output (CMOS);
there are other modes in which these pins
are not CMOS digital outputs; see Table 54,
Register 0x017, Register 0x01A, and
Register 0x01B
Applies when mux is set to any divider or
counter output, or PFD up/down pulse; also
applies in analog lock detect mode; usually
debug mode only; beware that spurs may
couple to output when any of these pins are
toggling
On-chip capacitance; used to calculate RC
time constant for analog lock detect readback;
use a pull-up resistor
Frequency above which the monitor always
indicates the presence of the reference
Frequency above which the monitor always
indicates the presence of the reference
Rev. E | Page 14 of 80