MT-023 Datasheet, PDF (6/11 Pages) Analog Devices – ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications

MT-023
Figure 8: AD1871 24-Bit, 96-kSPS Stereo Sigma-Delta ADC
Digital Filter Characteristics
In other applications, such as low frequency, high resolution 24-bit measurement Σ-Δ ADCs
(such as the AD77xx-series), other types of digital filters may be used. For instance, the SINC³
response is popular because it has zeros at multiples of the throughput rate. A 10-Hz throughput
rate produces zeros at 50 Hz and 60 Hz which aids in ac power line rejection.
Regardless of the type of digital filter, Σ-Δ ADCs require that sufficient settling time is allowed
after the application of a step function input.
MULTISTAGE NOISE SHAPING (MASH) SIGMA-DELTA CONVERTERS
As has been discussed, nonlinear stabilization techniques can be difficult for 3^rd order loops or
higher. In many cases, the multi-bit architecture is preferable. An alternative approach to either
of these, called multistage noise shaping (MASH), utilizes cascaded stable first-order loops (see
References 8 and 9). Figure 9 shows a block diagram of a three-stage MASH ADC. The output
of the first integrator is subtracted from the first DAC output to yield the first stage quantization
noise, Q1. Q1 is then quantized by the second stage. The output of the second integrator is
subtracted from the second DAC output to yield the second stage quantization noise which is in
turn quantized by the third stage.
The output of the first stage is summed with a single digital differentiation of the second stage
output and a double differentiation of the third stage output to yield the final output. The result
is that the quantization noise Q1 is suppressed by the second stage, and the quantization noise Q2
is suppressed by the third stage yielding the same suppression as a third-order loop. Since this
result is obtained using three first-order loops, stable operation is assured.
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