MT-023 Datasheet, PDF (3/11 Pages) Analog Devices – ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications

MT-023
Figure 4: Idling Patterns for Second-Order Sigma-Delta Modulator
(Integrator Output)
HIGHER ORDER LOOP CONSIDERATIONS
In order to achieve wide dynamic range, Σ-Δ modulator loops greater than second-order are
necessary, but present real design challenges. First of all, the simple linear models previously
discussed are no longer fully accurate. Loops of order greater than two are generally not
guaranteed to be stable under all input conditions. The instability arises because the comparator
is a nonlinear element whose effective "gain" varies inversely with the input level. This
mechanism for instability causes the following behavior: if the loop is operating normally, and a
large signal is applied to the input that overloads the loop, the average gain of the comparator is
reduced. The reduction in comparator gain in the linear model causes loop instability. This
causes instability even when the signal that caused it is removed.
In actual practice, such a circuit would normally oscillate on power-up due to initial conditions
caused by turn-on transients. The AD1879 dual audio ADC released in 1994 by Analog Devices
used a 5^th order loop. Extensive nonlinear stabilization techniques were required in this and
similar higher-order loop designs (References 1-5).
MULTI-BIT SIGMA-DELTA CONVERTERS
So far we have considered only Σ-Δ converters which contain a single-bit ADC (comparator) and
a single-bit DAC (switch). The block diagram of Figure 5 shows a multi-bit Σ-Δ ADC which
uses an n-bit flash ADC and an n-bit DAC. Obviously, this architecture will give a higher
dynamic range for a given oversampling ratio and order of loop filter. Stabilization is easier,
since second-order loops can generally be used. Idling patterns tend to be more random thereby
minimizing tonal effects.
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