EVAL-ADM1185EBZ_15 Datasheet, PDF (6/12 Pages) Analog Devices – Quad Voltage Monitor and Sequencer Evaluation Kit

EVAL-ADM1185EBZ
OBSERVING FAULT CONDITIONS
FOLLOWING POWER ON
If all four supply voltages are above their associated threshold,
PWRGD asserts and the logical core latches into a different
mode of operation. If the 3.3 V supply monitored by VIN1
faults while the device is in the power-good state, the PWRDG
output is deasserted and all of the outputs are immediately
turned off. If a supply monitored by VIN2 to VIN4 fails, the
PWRGD output is deasserted, but the other outputs are not
deasserted.
Fault conditions may be investigated by using the four rotary
switches, VR1 to VR4. By turning a rotary switch clockwise, the
associated input voltage is reduced.
Rotary Switch VR1 controls the voltage at Input VIN1. As VR1
is turned clockwise, this voltage is reduced. When the voltage at
Input Pin VIN1 drops below 0.6 V, OUT1 is switched to
ground, disabling Regulator U1. In addition, VIN2 can no
longer detect the 2.5 V supply and, in turn, OUT2 and OUT3
are deasserted. As a result, the PWRGD output is also
deasserted. The LEDs clearly indicate the status of the four
voltage supplies and PWRGD.
Preliminary Technical Data
Similarly, if PWRGD has been asserted and one of the rotary
switches, VR2 to VR4, is turned clockwise, reducing the voltage
at the associated input pin to below 0.6 V, the PWRGD output is
deasserted, but the other outputs are not deasserted. The LEDs
provide a clear indication of the status of each of the inputs and
PWRGD.
ADDITIONAL DELAYS
It is possible to introduce additional delays by connecting a
capacitor to the input pins, VIN1 to VIN4. For example if a
capacitor is placed on the VIN2 pin, the rise of the voltage on
that pin will slow, effectively setting a time delay between the
2.5 V rail powering up and the next regulator becoming
enabled. Switches S3, S4, S5, and S6 conveniently allow the user
to introduce time delays to each of the four inputs.
2.5V
130kΩ
ADM1185
VIN
46.4kΩ 1µF
Figure 3. Introduction of Additional Delay
Rev. PrA | Page 6 of 12