ADV7310 Datasheet, PDF (6/84 Pages) Analog Devices – Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs

ADV7310/ADV7311
TIMING SPECIFICATIONS (V_AA = 2.375 V–2.625 V, V_DD = 2.375 V–2.625 V; V_{DD_IO} = 2.375 V–3.6 V, V_REF = 1.235 V, R_SET = 3040 ⍀,
R_LOAD = 300 ⍀. All specifications T_MIN to T_MAX (0؇C to 70؇C), unless otherwise noted.)
Parameter
Min Typ Max Unit
Test Conditions
MPU PORT¹
SCLOCK Frequency
0
SCLOCK High Pulsewidth, t₁
0.6
SCLOCK Low Pulsewidth, t₂
1.3
Hold Time (Start Condition), t₃
0.6
Setup Time (Start Condition), t₄
0.6
Data Setup Time, t₅
100
SDATA, SCLOCK Rise Time, t₆
SDATA, SCLOCK Fall Time, t₇
Setup Time (Stop Condition), t₈
0.6
RESET Low Time
100
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
First clock generated after this period
relevant for repeated start condition
ANALOG OUTPUTS
Analog Output Delay²
Output Skew
7
ns
1
ns
CLOCK CONTROL AND PIXEL PORT³
f_CLK
f_CLK
Clock High Time, t₉
Clock Low Time, t₁₀
Data Setup Time, t₁₁₁
Data Hold Time, t₁₂₁
SD Output Access Time, t₁₃
SD Output Hold Time, t₁₄
HD Output Access Time, t₁₃
HD Output Hold Time, t₁₄
81
40
40
2.0
2.0
5.0
5.0
PIPELINE DELAY⁴
63
76
35
41
36
27
MHz
Progressive scan mode
MHz
HDTV mode/async mode
% of one clk cycle
% of one clk cycle
ns
ns
15
ns
ns
14
ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD [2Ï«, 16Ï«]
SD component mode [16Ï«]
PS [1Ï«]
PS [8Ï«]
HD[2Ï«, 1Ï«]
NOTES
1_{Guaranteed by characterization.}
2_{Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.}
3_{Data: C[9:0]; Y[9:0], S[9:0]}
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
4_{SD, PS = 27 MHz, HD = 74.25 MHz.}
Specifications subject to change without notice.
–6–
REV. A