ADV7192 Datasheet, PDF (6/69 Pages) Analog Devices – Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs

ADV7192
5 V TIMING CHARACTERISTICS (VAA = 5 V ؎ 250 mV, VREF = 1.235 V, RSET1,2 = 1200 V unless otherwise noted. All
specifications T_MIN to T_MAX1 unless otherwise noted.)
Parameter
Min Typ Max Unit
Test Conditions
MPU PORT²
SCLOCK Frequency
SCLOCK High Pulsewidth, t₁
SCLOCK Low Pulsewidth, t₂
Hold Time (Start Condition), t₃
Setup Time (Start Condition), t₄
Data Setup Time, t₅
SDATA, SCLOCK Rise Time, t₆
SDATA, SCLOCK Fall Time, t₇
Setup Time (Stop Condition), t₈
ANALOG OUTPUTS²
Analog Output Delay
DAC Analog Output Skew
0
400 kHz
0.6
µs
1.3
µs
0.6
µs
0.6
µs
100
ns
300 ns
300 ns
0.6
µs
8
ns
0.1
ns
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
CLOCK CONTROL AND PIXEL
PORT³
f_CLOCK
Clock High Time, t₉
8
Clock Low Time, t₁₀
8
Data Setup Time, t₁₁
6
Data Hold Time, t₁₂
5
Control Setup Time, t₁₁
6
Control Hold Time, t₁₂
4
Digital Output Access Time, t₁₃
Digital Output Hold Time, t₁₄
Pipeline Delay, t₁₅ (2× Oversampling)
Pipeline Delay, t₁₅ (4× Oversampling)
TELETEXT PORT⁴
Digital Output Access Time, t₁₆
Data Setup Time, t₁₇
Data Hold Time, t₁₈
RESET CONTROL
RESET Low Time
27
2
3
2.5
2.0
13
12
57
67
11
3
6
3
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
ns
ns
ns
ns
PLL²
PLL Output Frequency
54
MHz
NOTES
1_{Temperature range TMIN to TMAX: 0°C to 70°C.}
2_{Guaranteed by characterization.}
3_{Pixel Port consists of:}
Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN
4_{Teletext Port consists of:}
Digital Output: TTXRQ
Data: TTX
Specifications subject to change without notice.
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