ADSP-2188M_15 Datasheet, PDF (6/40 Pages) Analog Devices – DSP Microcomputer

ADSP-2188M
Common-Mode Pins
Pin Name
# of Pins
I/O
Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
1
I
Processor Reset Input
1
I
Bus Request Input
1
O
Bus Grant Output
1
O
Bus Grant Hung Output
1
O
Data Memory Select Output
1
O
Program Memory Select Output
1
O
Memory Select Output
1
O
Byte Memory Select Output
1
O
Combined Memory Select Output
1
O
Memory Read Enable Output
1
O
Memory Write Enable Output
IRQ2
PF7
IRQL1
PF6
1
I
Edge- or Level-Sensitive Interrupt Request¹
I/O
Programmable I/O Pin
1
I
Level-Sensitive Interrupt Requests¹
I/O
Programmable I/O Pin
IRQL0
PF5
IRQE
PF4
Mode D
PF3
Mode C
PF2
Mode B
PF1
Mode A
PF0
1
I
Level-Sensitive Interrupt Requests¹
I/O
Programmable I/O Pin
1
I
Edge-Sensitive Interrupt Requests¹
I/O
Programmable I/O Pin
1
I
Mode Select Input—Checked Only During RESET
I/O
Programmable I/O Pin During Normal Operation
1
I
Mode Select Input—Checked Only During RESET
I/O
Programmable I/O Pin During Normal Operation
1
I
Mode Select Input—Checked Only During RESET
I/O
Programmable I/O Pin During Normal Operation
1
I
Mode Select Input—Checked Only During RESET
I/O
Programmable I/O Pin During Normal Operation
CLKIN, XTAL
2
I
Clock or Quartz Crystal Input
CLKOUT
1
O
Processor Clock Output
SPORT0
5
I/O
Serial Port I/O Pins
SPORT1
5
IRQ1:0, FI, FO
PWD
1
I/O
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO²
I
Power-Down Control Input
PWDACK
1
O
Power-Down Control Output
FL0, FL1, FL2
3
O
Output Flags
V_DDINT
V_DDEXT
GND
2
I
4
I
10
I
Internal V_DD (2.75 V) Power (LQFP)
External V_DD (2.75 V or 3.3 V) Power (LQFP)
Ground (LQFP)
V_DDINT
V_DDEXT
GND
4
I
7
I
20
I
Internal V_DD (2.75 V) Power (Mini-BGA)
External V_DD (2.75 V or 3.3 V) Power (Mini-BGA)
Ground (Mini-BGA)
EZ-Port
9
I/O
For Emulation Use
NOTES
1_{Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt}
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2_{SPORT configuration determined by the DSP System Control Register. Software configurable.}
–6–
REV. 0