ADSP-2188M_15 Datasheet, PDF (26/40 Pages) Analog Devices – DSP Microcomputer

ADSP-2188M
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
t_BH
BR Hold after CLKOUT High¹
t_BS
BR Setup before CLKOUT Low¹
0.25t_CK + 2
ns
0.25t_CK + 10
ns
Switching Characteristics:
t_SD
t_SDB
t_SE
t_SEC
t_SDBH
t_SEH
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low²
BGH High to xMS, RD, WR Enable²
0
0
0.25t_CK – 3
0
0
0.25t_CK + 8
ns
ns
ns
ns
ns
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1_{BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on}
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2_{BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.}
t_BH
CLKOUT
BR
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
t_BS
t_SD
t_SEC
t_SDB
t_SE
t_SDBH
t_SEH
Figure 23. Bus Request–Bus Grant
–26–
REV. 0