AD9520-1 Datasheet, PDF (6/84 Pages) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO

AD9520-1
Parameter
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
PLL DIGITAL LOCK DETECT WINDOW²
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)²
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Min
560
−320
140
−460
Typ Max
1060 1310
+50 +240
630 870
−20 +200
−165
−162
−152
−144
−222
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
ps
When N delay and R delay are bypassed
ps
When N delay = Setting 110 and R delay is bypassed
ps
When N delay and R delay are bypassed
ps
When N delay = Setting 011 and R delay is bypassed
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 12
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings; lock
detect window settings can be varied by changing the
CPRSET resistor
Selected by 0x017[1:0] and 0x018[4] (this is the threshold
to go from unlock to lock)
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
Selected by 0x017[1:0] and 0x018[4] (this is the threshold
to go from lock to unlock)
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
1 _{The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.}
2 _{For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.}
Rev. 0 | Page 6 of 84