AD9520-1 Datasheet, PDF (1/84 Pages) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO

12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2.5 GHz VCO
AD9520-1
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.27 GHz to 2.65 GHz
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.67 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Auto and manual reference switchover/holdover modes,
with selectable revertive/nonrevertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 has a 1-to-32 divider with phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs <16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-1¹ provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz
to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
CP
LF
OPTIONAL
REFIN
REFIN
CLK
REF1
REF2
DIVIDER
AND MUXES
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
STATUS
MONITOR
VCO
ZERO
DELAY
LVPECL/
CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
SPI/I²C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9520
Figure 1.
The AD9520 serial interface supports both SPI and I2C® ports.
An in-package EEPROM can be programmed through the
serial interface and store user-defined register settings for
power-up and chip reset.
The AD9520 features 12 LVPECL outputs in four groups. Any
of the 1.6 GHz LVPECL outputs can be reconfigured as two
250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9520 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V. A separate output driver power
supply can be from 2.375 V to 3.465 V.
The AD9520 is specified for operation over the standard industrial
range of −40°C to +85°C.
1 _{The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-1 is used, it is referring to that specific}
member of the AD9520 family.
Rev. 0
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