AD9518-1 Datasheet, PDF (6/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 2.5 GHz VCO

AD9518-1
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Input Sensitivity, Differential
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Min
Typ
Max
Unit
Test Conditions/Comments
Differential input
0¹
2.4
GHz
High frequency distribution (VCO divider)
0¹
1.6
GHz
Distribution only (VCO divider bypassed)
150
mV p-p Measured at 2.4 GHz; jitter performance is
improved with slew rates > 1 V/ns
2
V p-p Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
1.3
1.57
1.8
V
Self-biased; enables ac coupling
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
150
mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground
3.9
4.7
5.7
kΩ
Self-biased
2
pF
1 _{Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.}
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
2950
Max
Unit
MHz
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
V VS_LVPECL − VS_LVPECL − VS_LVPECL −
1.12
0.98
0.84
V VS_LVPECL − VS_LVPECL − VS_LVPECL −
2.03
1.77
1.49
550
790
980
mV
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 16 for peak-to-peak
differential amplitude
This is VOH − VOL for each leg of a differential pair for
default amplitude setting with driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver toggling
is roughly 2× these values (see Figure 16 for variation
over frequency)
TIMING CHARACTERISTICS
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 50 Ω to VS − 2 V; level = 810 mV
Output Rise Time, tRP
70
180
ps
20% to 80%, measured differentially
Output Fall Time, tFP
70
180
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL
OUTPUT
High Frequency Clock Distribution
835
995
1180 ps
Configuration
See Figure 28
Clock Distribution Configuration
773
933
1090 ps
See Figure 30
Variation with Temperature
0.8
ps/°C
OUTPUT SKEW, LVPECL OUTPUTS¹
LVPECL Outputs That Share the Same
Divider
5
15
ps
LVPECL Outputs on Different Dividers
13
40
ps
All LVPECL Outputs Across Multiple Parts
220
ps
1 _{This is the difference between any two similar delay paths while operating at the same voltage and temperature.}
Rev. C | Page 6 of 64