AD9518-1 Datasheet, PDF (46/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 2.5 GHz VCO

AD9518-1
Data Sheet
Reg.
Addr.
(Hex)
Parameter
LVPECL Outputs
0x0F0 OUT0
Bit 7 (MSB) Bit 6
Bit 5
Blank
0x0F1 OUT1
Blank
0x0F2 OUT2
Blank
0x0F3 OUT3
Blank
0x0F4 OUT4
Blank
0x0F5 OUT5
Blank
0x0F6
to
0x13F
0x140
to
0x143
0x144
to
0x18F
LVPECL Channel Dividers
0x190 Divider 0
(PECL)
Divider 0 low cycles
0x191
Divider 0
bypass
Divider 0 Divider 0
nosync
force high
0x192
Blank
0x193
0x194
Divider 1
(PECL)
0x195
Divider 1 low cycles
Divider 1
bypass
Divider 1
nosync
Blank
Divider 1
force high
0x196
0x197
Divider 2
(PECL)
0x198
Divider 2 low cycles
Divider 2
bypass
Divider 2
nosync
Blank
Divider 2
force high
0x199
to
0x1A3
0x1A4
to
0x1DF
VCO Divider and CLK Input
0x1E0 VCO divider
0x1E1 Input CLKs
Blank
Reserved
0x1E2
to
0x22A
Bit 4
Bit 3
Bit 2
OUT0
invert
OUT1
invert
OUT2
invert
OUT3
invert
OUT4
invert
OUT5
invert
Blank
OUT0 LVPECL
differential voltage
OUT1 LVPECL
differential voltage
OUT2 LVPECL
differential voltage
OUT3 LVPECL
differential voltage
OUT4 LVPECL
differential voltage
OUT5 LVPECL
differential voltage
Reserved
Blank
Bit 1
Bit 0 (LSB)
OUT0 power-down
OUT1 power-down
OUT2 power-down
OUT3 power-down
OUT4 power-down
OUT5 power-down
Divider 0
start high
Reserved
Divider 1
start high
Reserved
Divider 2
start high
Reserved
Reserved
Blank
Divider 0 high cycles
Divider 0 phase offset
Divider 0
direct to
output
Divider 1 high cycles
Divider 1 phase offset
Divider 1
direct to
output
Divider 2 high cycles
Divider 2 phase offset
Divider 2
direct to
output
Divider 0
DCCOFF
Divider 1
DCCOFF
Divider 2
DCCOFF
Reserved
Power
down
clock input
section
Power down
VCO clock
interface
Blank
Power
down VCO
and CLK
VCO Divider
Select
Bypass VCO
VCO or CLK divider
Default
Value
(Hex)
0x08
0x0A
0x08
0x0A
0x08
0x0A
0x00
0x80
0x00
0xBB
0x00
0x00
0x00
0x00
0x00
0x02
0x00
Rev. C | Page 46 of 64