AD7875_15 Datasheet, PDF (6/28 Pages) Analog Devices – LC MOS Complete, 12-Bit, 100 kHz, Sampling ADCs

AD7870/AD7875/AD7876
TIMING CHARACTERISTICS
VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17. Timing specifications are
sample tested at 25°C to ensure compliance, unless otherwise noted. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V)
and timed from a voltage level of 1.6 V.
Table 3.
Parameter¹
t1
t2
t3 ²
t4
t5
t62, ³
t72, ⁴
t8
t9
t10
t11 ⁵
t12 ⁶
t13
t14
t15
t16
t17
t18
t19
t20
Limit at TMIN, TMAX
(J, K, L, A, B, C Versions)
50
0
60
0
70
57
5
50
0
0
100
370
135
20
100
10
100
60
120
200
0
0
0
Limit at TMIN, TMAX
(T Version)
50
0
75
0
70
70
5
50
0
0
100
370
150
20
100
10
100
60
120
200
0
0
0
Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
Conditions/Comments
CONVST pulse width
CS to RD setup time (Mode 1)
RD pulse width
CS to RD hold time (Mode 1)
RD to INT delay
Data access time after RD
Bus relinquish time after RD
HBEN to RD setup time
HBEN to RD hold time
SSTRB to SCLK falling edge setup time
SCLK cycle time
SCLK to valid data delay. CL = 35 pF
SCLK rising edge to SSTRB
Bus relinquish time after SCLK
CS to RD setup time (Mode 2)
CS to BUSY propagation delay
Data setup time prior to BUSY
CS to RD hold time (Mode 2)
HBEN to CS setup time
HBEN to CS hold time
1 _{Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.}
2 _{Timing specifications for t3, t6, and for the maximum limit at t7 are 100% production tested.}
3 _{t6 is measured with the load circuits of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.}
4 _{t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 5.}
5 _{SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.}
6 _{SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩ||CL) and thus the time to reach 2.4 V.}
Rev. C | Page 6 of 28