AD7761 Datasheet, PDF (6/69 Pages) Analog Devices – 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW

AD7761
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
LVDS Clock²
RL = 100 Ω
Differential Input Voltage
100
650
mV
Common-Mode Input Voltage
800
1575
mV
Absolute Input Voltage
1.88
V
ADC RESET²
ADC Start-Up Time After Reset⁶
Time to first DRDY, fast mode,
decimation by 32
1.58
1.66
ms
Minimum RESET Low Pulse Width
tMCLK = 1/MCLK
2 × tMCLK
LOGIC INPUTS
Input Voltage²
High, VINH
0.65 ×
V
IOVDD
Low, VINL
Hysteresis²
2.25 V < IOVDD < 3.6 V
1.72 V < IOVDD < 1.88 V
2.25 V < IOVDD < 3.6 V
0.04
0.7
V
0.4
V
0.09
V
1.72 V < IOVDD < 1.88 V
0.04
0.2
V
Leakage Current
RESET pin⁷
−10
+0.03
+10
μA
−10
+10
μA
LOGIC OUTPUTS
Output Voltage²
High, VOH
ISOURCE = 200 μA
0.8 ×
V
IOVDD
Low, VOL
ISINK = 400 μA
0.4
V
Leakage Current
Floating state
−10
+10
μA
Output Capacitance
Floating state
10
pF
SYSTEM CALIBRATION²
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
−1.05 × VREF
0.4 × VREF
1.05 × VREF
V
V
2.1 × VREF
V
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS
4.5
5.0
5.5
V
AVDD2 − AVSS
2.0
2.25 to 5.0 5.5
V
AVSS − DGND
−2.75
0
V
IOVDD − DGND
1.72
1.8 or 2.5 to 3.6
V
3.3
POWER SUPPLY CURRENTS
Maximum output data rate, CMOS
MCLK, eight DOUTx signals, all
supplies at maximum voltages, all
channels in Channel Mode A
Eight Channels Active
Fast Mode
AVDD1 Current
Precharge reference buffers off/on
36/57.5
40/64
mA
AVDD2 Current
37.5
40
mA
IOVDD Current
Wideband filter
Sinc5 filter²
63
69
mA
27
29
mA
Median Mode
AVDD1 Current
Precharge reference buffers off/on
18.5/29
mA
AVDD2 Current
21.3
mA
IOVDD Current
Wideband filter
34
mA
Sinc5 filter
16
mA
Rev. 0 | Page 6 of 69