AD7761 Datasheet, PDF (46/69 Pages) Analog Devices – 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW

AD7761
AD7761
CHANNEL0 TO CHANNEL7 ^IOVDD
OUTPUT ON DOUT0 1
1
FORMAT0
FORMAT1
DRDY
DCLK
DOUT0
Data Sheet
DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT
Figure 68. FORMATx = 10 or 11, One Data Output Pin
ADC CONVERSION OUTPUT: HEADER AND DATA
The AD7761 data is output on the DOUT0 to DOUT7 pins,
depending on the FORMATx pins. The actual structure of the
data output for each ADC result is shown in Figure 69. Each
ADC result comprises 24 bits. The first eight bits are the header
status bits, which contain status information and the channel
number. The names of each of the header status bits are shown
in Table 29, and their functions are explained in the subsequent
sections. This header is followed by a 16-bit ADC output in
twos complement coding, MSB first.
Transitions on the DRDY and the DOUTx pins are aligned with
the rising edge of DCLK. See Figure 2 and Table 2 for details.
wideband and sinc5 filters are shown in Table 31 and Table 32,
respectively. This bit is set if this settling delay has not yet elapsed.
Repeated Data
If different channels use different decimation rates, data outputs
are repeated for the slower speed channels. In these cases, the
header is output as normal with the repeated data bit set to 1,
and the following repeated ADC result is output as all zeros.
This bit indicates that the conversion result of all zeros is not
real; it indicates that there is a repeated data condition because
two different decimation rates are selected. This condition can
only occur during SPI control of the AD7761.
Filter Type
DRDY
DOUTx N – 1
HEADER N
ADC DATA N
8 BITS
16 BITS
Figure 69. ADC Output: 8-Bit Header, 16-Bit ADC Conversion Data
Table 29. Header Status Bits
Bit
Bit Name
7
CHIP_ERROR
6
Filter not settled
5
Repeated data
4
Filter type
3
Filter saturated
[2:0]
Channel ID[2:0]
Chip Error
The chip error bit indicates that a serious error has occurred. If
this bit is set, a reset is required to clear this bit. This bit indicates
that the external clock is not detected, a memory map bit has
unexpectedly changed state, or an internal CRC error has been
detected.
In the case where an external clock is not detected, the conversion
results are output as all zeros regardless of the analog input
voltages applied to the ADC channels.
Filter Not Settled
After power-up, reset, or synchronization, the AD7761 clears the
digital filters and begins conversion. Due to the weighting of the
digital filters, there is a delay from the first conversion to fully
settled data. The settling times for the AD7761 when using the
In pin control mode, all channels operate using one filter
selection. The filter selected in pin control mode is determined
by the logic level of the FILTER pin. In SPI control mode, the
digital filters can be selected on a per channel basis, using the
mode registers. This header bit is 0 for channels using the
wideband filter, and 1 for channels using the sinc5 filter.
Filter Saturated
The filter saturated bit indicates that the filter output is clipping at
either positive or negative full scale. The digital filter clips if the
signal goes beyond the specification of the filter; it does not wrap.
The clipping may be caused by the analog input exceeding the
analog input range, or by a step change in the input, which may
cause overshoot in the digital filter. Clipping may also occur
when the combination of the analog input signal and the channel
gain register setting causes the signal seen by the filter to be
higher than the analog input range.
Channel ID
The channel ID bits indicate the ADC channel from which the
succeeding conversion data originates (see Table 30).
Table 30. Channel ID vs. Channel Number
Channel Channel ID 2 Channel ID 1
Channel 0 0
0
Channel 1 0
0
Channel 2 0
1
Channel 3 0
1
Channel 4 1
0
Channel 5 1
0
Channel 6 1
1
Channel 7 1
1
Channel ID 0
0
1
0
1
0
1
0
1
Rev. 0 | Page 46 of 69