AD4000 Datasheet, PDF (6/33 Pages) Analog Devices – 16-Bit, 2 MSPS Precision Pseudo Differential ADC

Data Sheet
AD4000
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted.¹
Table 2. Digital Interface Timing
Parameter
Conversion Time—CNV Rising Edge to Data Available
Acquisition Phase²
Time Between Conversions
CNV Pulse Width (CS Mode)³
SCK Period (CS Mode)⁴
VIO > 2.7 V
VIO > 1.7 V
SCK Period (Daisy-Chain Mode)⁵
VIO > 2.7 V
VIO > 1.7 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid Delay
SCK Falling Edge to Data Valid Delay
VIO > 2.7 V
VIO > 1.7 V
CNV or SDI Low to SDO D15 MSB Valid Delay (CS Mode)
VIO > 2.7 V
VIO > 1.7 V
CNV Rising Edge to First SCK Rising Edge Delay
Last SCK Falling Edge to CNV Rising Edge Delay⁶
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode)
SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode)
SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
290
500
10
9.8
12.3
20
25
3
3
1.5
tEN
tQUIET1
tQUIET2
tDIS
tSSDICNV
tHSDICNV
tHSCKCNV
tSSDISCK
tHSDISCK
190
60
2
2
12
2
2
Typ Max Unit
290 320 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.5
ns
10.5 ns
10
ns
13
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
1 _{See Figure 2 for the timing voltage levels.}
2 _{The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.}
3 _{For turbo mode, tCNVH must match the tQUIET1 minimum.}
4 _{A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz.}
5 _{A 50% duty cycle is assumed for SCK.}
6 _{See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2.}
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