AD4000 Datasheet, PDF (16/33 Pages) Analog Devices – 16-Bit, 2 MSPS Precision Pseudo Differential ADC

Data Sheet
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the IN+ and IN− inputs captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and VREF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4, …, VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the control logic generates the ADC output code and a busy
signal indicator.
Because the AD4000 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer characteristics for the AD4000 are shown in
Figure 30 and Table 9.
111...111
111...110
111...101
AD4000
Table 9. Output Codes and Ideal Input Voltages
Description
Analog
Input,
VREF = 5 V
VREF = 5 V
with Span
Compression
Enabled (V)
FSR − 1 LSB
4.999924 V 4.499939
Midscale + 1 LSB 2.500076 V 2.500061
Midscale
2.5 V
2.5
Midscale − 1 LSB 2.499924 V 2.499939
−FSR + 1 LSB
76.3 μV
0.50006103
−FSR
0V
0.5
Digital
Output
Code
(Hex)
FFFF¹
8001
8000
7FFF
0001
0000²
1 _{This output code is also the code for an overranged analog input (VIN+ − VIN−}
above VREF − 0 V).
2 _{This output code is also the code for an underranged analog input (VIN+ −}
VIN− below 0 V).
000...010
000...001
000...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 30. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
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