AD9371 Datasheet, PDF (59/60 Pages) Analog Devices – Dual differential transmitters

Data Sheet
AD9371
Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD Lane Rates)
Tx/Tx Synthesis/
Tx Input
Rx Output JESD204B Lane Rate JESD204B (No.
Rx Bandwidth (MHz) Rate (MSPS) Rate (MSPS) (Mbps), Two Tx/Two Rx of Lanes) Tx/Rx
100/250/100
307.2
153.6
6144
4/2
75/200/100
245.76
122.88
4915.2
4/2
20/100/40
122.88
61.44
2457.6
4/2
20/100/20
122.88
30.72
2457.6
4/1
Reference Clock Options (MHz)
122.88, 153.6, 245.76, 307.2
122.88, 245.76
122.88, 245.76
122.88, 245.76
I/Q DAC
DEC5
TRANSMITTER
HALF-BAND
FILTER 2
TRANSMITTER
HALF-BAND
FILTER 1
TRANSMITTER FIR
(INTERPOLATION
1, 2, 4)
QUADRATURE
ERROR
CORRECTION
Figure 240. Example Tx Data Path Filter Implementation
DIGITAL
GAIN
JESD204B
ADC
RECEIVER
HALF-BAND
FILTER 3
RECEIVER
HALF-BAND
FILTER 2
RECEIVER
HALF-BAND
FILTER 1
RFIR
(DECIMATION
1, 2, 4)
QEC
CORRECTION
FILTER
DIGITAL
GAIN
Figure 241. Data Rx Data Path Filter Implementation
DC
CORRECTION
JESD204B
POWER SUPPLY SEQUENCE
The AD9371 requires a specific power-up sequence to avoid
undesired power-up currents. The optimal power-on sequence
starts the process by powering up the VDIG and the VDDA_1P3
(analog) supplies simultaneously. If they cannot power up
simultaneously, the VDIG supply must power up first. The
VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies
must then power up after the VDIG and VDDA_1P3 supplies.
Note that the VDD_IF supply can power up at any time. It is
also recommended to toggle the RESET signal after power has
stabilized prior to configuration. Follow the reverse order of
the power-up sequence to power-down.
Note that VDDA_1P3 refers to all analog 1.3 V supplies
including the following: VDDA_BB, VDDA_CLKSYNTH,
VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH,
VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH,
VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH,
VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
JTAG BOUNDARY SCAN
The AD9371 provides support for a JTAG boundary scan.
There are five dual-function pins associated with the JTAG
interface. These pins, listed in Table 9, are used to access the
on-chip test access port. To enable the JTAG functionality,
set the GPIO_0 through GPIO_3 pins according to Table 10
depending on how the desired JESD204B sync pin (that is,
SYNCINB0+, SYNCINB0−, SYNCINB1+, SYNCINB1−,
SYNCBOUTB0+, or SYNCBOUTB0−) is configured in the
software (LVDS or CMOS mode). Pull the TEST pin high to
enable the JTAG mode.
Table 9. Dual-Function Boundary Scan Test Pins
Mnemonic JTAG Mnemonic Description
GPIO_4
TRST
Test access port reset
GPIO_5
TDO
Test data output
GPIO_6
TDI
Test data input
GPIO_7
TMS
Test access port mode select
GPIO_18 TCK
Test clock
Table 10. JTAG Modes
Test Pin Level GPIO_0 to GPIO_3
0
XXXX¹
1
1001
1
1011
1 _{X means don’t care.}
Description
Normal operation
JTAG mode with LVDS
JESD204B sync signals
JTAG mode with CMOS
JESD204B sync signals
Rev. A | Page 59 of 60