ADUC7032-8L_15 Datasheet, PDF (58/120 Pages) Analog Devices – Integrated Precision Battery Sensor for Automotive System

ADuC7032-8L
ADC Calibration
As described in detail in the top level diagrams (Figure 15 and
Figure 16), the signal flow through all ADC channels can be
described in simple terms.
1. An input voltage is applied through an input buffer (and
PGA in the case of the I-ADC) to the Σ-Δ modulator.
2. The modulator output is applied to a programmable digital
decimation filter.
3. The filter output result is then averaged if chopping is used.
4. An offset value (ADCxOF) is subtracted from the result.
5. This result is scaled by a gain value (ADCxGN).
6. Finally, the result is formatted as twos complement/offset
binary, rounded to 16 bits, or clamped to ±full scale.
Each ADC has a specific offset and gain correction or calibration
coefficient associated with it that is stored in MMR-based offset
and gain registers (ADCxOF and ADCxGN). The offset and
gain registers can be used to remove offset and gain errors
arising within the part, as well as system-level offset and gain
errors external to the part.
These registers are configured at power-on with a factory-
programmed calibration value. These factory calibration values
vary from part to part, reflecting the manufacturing variability of
internal ADC circuits. However, these registers can also be
overwritten by user code (only if the ADC is in idle mode) and
are automatically overwritten if an offset or gain calibration cycle
is initiated by the user via the mode bits in the ADCMDE[2:0]
MMR. Two types of automatic calibration are available to the user.
Self- (Offset or Gain) Calibration
The ADC generates its calibration coefficient based on an
internally generated 0 V in the case of self-offset calibration,
and full-scale voltage in the case of self-gain calibration. It should
be emphasized that ADC self-calibrations correct for offset and
gain errors within the ADC. Self-calibrations cannot compensate
for other external errors in the system, for example, shunt-
resistor tolerance/drift, external offset voltages, and so on.
System (Offset or Gain) Calibration
The ADC generates its calibration coefficient based on an exter-
nally generated zero-scale voltage in the case of system-offset
calibration and full-scale voltage in the case of system-gain
calibration, which are applied to the external ADC input for the
duration of the calibration cycle.
The duration of an offset calibration is one single conversion
cycle (3/fADC chop off, 2/fADC chop on) before returning the
ADC to idle mode. A gain calibration is a two-stage process
that, subsequently, takes twice as long as an offset calibration
cycle. Once a calibration cycle is initiated, any ongoing ADC
conversion is immediately halted, the calibration is carried out
automatically at an ADC update rate programmed into ADCFLT,
and the ADC is always returned to idle after any calibration
cycle. It is strongly recommended that ADC calibration be
initiated at as low an ADC update rate as possible (high SF
value in ADCFLT) to minimize the impact of ADC noise
during calibration.
Note that in self-calibration mode, ADC0GN must first contain
the values for PGA = 1 before a calibration scheme is started.
Using the Offset and Gain Calibration Registers
If the chop bit (ADCFLT[15]) is enabled, internal ADC offset
errors are minimized, and an offset calibration may not be
required. If chopping is disabled however, an initial offset
calibration is required and may need to be repeated, particularly
after a large change in temperature.
A gain calibration, particularly in the context of the I-ADC
(with internal PGA) may need to be carried out at all relevant
system gain ranges, depending on system accuracy requirements.
If it is not possible to apply an external full-scale current on all
gain ranges, it is possible to apply a lower current and scale the
result produced by the calibration. For example, apply a 50%
current and then divide the ADC0GN value produced by 2 and
write this value back into ADC0GN. Note that there is a lower
limit to the input signal that can be applied for a system calibration
because the ADC0GN register is only 16 bits. The input span
(the difference between the system zero-scale value and the
system full-scale value) should be greater than 40% of the
nominal full-scale input range, that is, >40% of VREF/GAIN.
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients that can be copied by user code directly
into the relevant calibration registers, as appropriate, based on
system configuration. In general, the simplest way to use the
calibration registers is to let the ADC calculate the values
required as part of the ADC automatic calibration modes.
Rev. A | Page 58 of 120