ADUC7032-8L_15 Datasheet, PDF (40/120 Pages) Analog Devices – Integrated Precision Battery Sensor for Automotive System

ADuC7032-8L
VOLTAGE CHANNEL ADC (V-ADC)
The V-ADC is intended to convert battery voltage. As with the
current channel ADC, described in the Current Channel ADC
(I-ADC) section, this ADC employs an identical Σ-Δ conversion
technique, including a modified Sinc3 low-pass filter to give
a valid 16-bit data conversion result at programmable output
rates from 4 Hz to 8 kHz. An external RC filter network is not
required because this is implemented internally in the voltage
channel.
The external battery voltage (VBAT) is routed to the ADC input
via an on-chip high voltage, resistive attenuator. This must be
enabled/disabled via HVCFG1[7].
The time to a first valid (fully settled) result on the voltage
channel is three ADC conversion cycles with chop mode turned
off, and two ADC conversion cycles with chop mode turned on.
This ADC is again buffered, but, unlike the current channel,
it has a fixed VBAT input range of 0 V to 28.8 V (assuming an
internal 1.2 V reference). A top level overview of this ADC
signal chain is shown in Figure 16.
TEMPERATURE CHANNEL ADC (T-ADC)
The T-ADC is designed to convert battery temperature. The
battery temperature can be derived via the on-chip temperature
sensor or an external temperature sensor input.
The time to a first valid (fully settled) result after an input
channel switch on the temperature channel is three ADC
conversion cycles with chop mode turned off and two ADC
conversion cycles with chop mode turned on.
As with the current and voltage channel ADCs, this ADC uses
an identical Σ-Δ conversion technique, including a modified
Sinc3 low-pass filter to give a valid 16-bit data conversion result
at programmable output rates from 4 Hz to 8 kHz.
DIFFERENTIAL
ATTENUATOR
DIVIDE BY 24, INPUT
ATTENUATOR.
BUFFER AMPLIFIERS
THE BUFFER AMPLIFIERS
PRESENT A HIGH
IMPEDANCE INPUT STAGE
FOR THE ANALOG INPUT.
ANALOG INPUT
PROGRAMMABLE CHOPPING
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE
CONVERSION CYCLE.
Σ-∆ MODULATOR
THE MODULATOR PROVIDES A
HIGH FREQUENCY 1-BIT DATA
STREAM (THE OUTPUT OF
WHICH IS ALSO CHOPPED) TO
THE DIGITAL FILTER, THE DUTY
CYCLE OF WHICH REPRESENTS
THE SAMPLED ANALOG INPUT
VOLTAGE.
Σ-∆ ADC
THE Σ-∆
ARCHITECTURE
ENSURES 16 BITS
NO MISSING CODES.
OUTPUT AVERAGE
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA-WORD OUTPUT FROM
THE FILTER IS SUMMED AND
AVERAGED WITH ITS
PREDECESSOR.
VBAT
45R*
2R*
1R*
BUF
CHOP
Σ-∆ ADC
Σ-∆
PROGRAMMABLE
MODULATOR DIGITAL FILTER
CHOP
INTERNAL
REFERENCE
OFFSET
COEFFICIENT
GAIN
COEFFICIENT
OUTPUT
AVERAGE
VREF
PRECISION REFERENCE
THE INTERNAL 5ppm/°C
REFERENCE IS ROUTED TO
THE ADC BY DEFAULT. AN
EXTERNAL REFERENCE ON
THE VREF PIN CAN ALSO
BE SELECTED.
OUTPUT SCALING
THE OUTPUT WORD FROM
THE DIGITAL FILTER IS
SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING
PROVIDED AS THE
CONVERSION RESULT.
OUTPUT
FORMAT
ADC
RESULT
*R = 60kΩ
PROGRAMMABLE
DIGITAL FILTER
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE VIA
THE ADCFLT MMR.
VOLTAGE
ADC
DATA MMR INTERRUPT
ADC INTERRUPT GENERATOR
GENERATES AN ADC
INTERRUPT ONCE A VOLTAGE
CONVERSION IS COMPLETE.
Figure 16. Voltage ADC, Top Level Overview
Rev. A | Page 40 of 120