ADV7182 Datasheet, PDF (57/96 Pages) Analog Devices – 10-Bit, SDTV Video Decoder with Differential Inputs

Data Sheet
ADV7182
Table 86. WST Packet Description
Packet
Header Packet (X/00)
Text Packets (X/01 to X/25)
8/30 (Format 1) Packet
Design Code = 0000 or 0001
UTC
8/30 (Format 2) Packet
Design Code = 0010 or 0011
PDC
X/26, X/27, X/28, X/29, X/30, X/31¹
Byte
1st
2nd
3rd
4th
5th to 10th
11th to 42nd
1st
2nd
3rd to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 42nd
Description
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Page number—Dehammed Byte 6
Page number—Dehammed Byte 7
Control bytes—Dehammed Byte 8 to Byte 13
Raw data bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Raw data bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
De-hammed initial teletext page, Byte 7 to Byte 12
UTC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Dehammed initial teletext page, Byte 7 to Byte 12
PDC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Raw data bytes
1 _{For X/26, X/28, and X/29, further decoding needs 24 × 18 hamming decoding. Not supported at present.}
VDP_CGMS_WSS_
VDP_CGMS_WSS_DATA_2 DATA_1[5:0]
RUN-IN START
SEQUENCE _CODE
01234567012345
ACTIVE
VIDEO
11.0µs
38.4µs
42.5µs
Figure 42. WSS Waveform
CGMS and WSS
The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC; therefore, the CGMS and WSS readback
registers are shared. WSS is biphase coded; the VDP performs a
biphase decoding to produce the 14 raw WSS bits in the CGMS/
WSS readback I²C registers and to set the CGMS_WSS_AVL bit.
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78[2],
Interrupt/VDP Map, Write Only, Self-Clearing
Setting CGMS_WSS_CLEAR to 0 does not reinitialize the
CGMS/WSS readback registers.
Setting CGMS_WSS_CLEAR to 1 reinitializes the CGMS/WSS
readback registers.
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78[2],
User Sub Map, Read Only
When CGMS_WSS_AVL is 0, CGMS/WSS was not detected.
When CGMS_WSS_AVL is 1, CGMS/WSS was detected.
VDP_CGMS_WSS_DATA_0[3:0], Address 0x7D[3:0];
VDP_CGMS_WSS_DATA_1[7:0], Address 0x7E[7:0];
VDP_CGMS_WSS_DATA_2[7:0], Address 0x7F[7:0];
Interrupt/VDP Map, Read Only
These bits hold the decoded CGMS or WSS data.
Refer to Figure 42 and Figure 43 for the I²C-to-WSS and I²C-to-
CGMS bit mapping.
Rev. A | Page 57 of 96