AD9789BBC Datasheet, PDF (57/76 Pages) Analog Devices – 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing

AD9789
Finally, when measuring performance for CMTS and other
digital TV applications, it is advantageous to insert a 1 dB,
1.2 GHz Chebyshev low-pass filter between the DAC and the
transformer to better control the impedance seen at the DAC
core. This helps to decrease the folded back harmonics for
higher frequency outputs. The optimal transformer for CMTS
measurements is the JTX-2-10T, which consists of a balun and
center-tapped transformer in a single package. This output stage
is shown in Figure 112.
IOUTP
70Ω
IOUTN
4.7pF
90Ω
90Ω
4.7pF
5.6nH
2.2pF
5.6nH
JTX-2-10T
Figure 112. Recommended Transformer Output Stage
for CMTS Measurements
Traces from the DAC to the transformer should be 50 Ω imped-
ance to ground each in Figure 110 and Figure 112 and 25 Ω to
ground each in Figure 111 to avoid unnecessary parasitics.
CLOCKING THE AD9789
To provide the required signal swing for the internal clock
receiver of the AD9789, it is necessary to use an external clock
buffer chip to drive the CLKP and CLKN inputs. These high
level, high slew rate signals should not be routed any distance
on a PCB. The recommended clock buffer for this application
is the ADCLK914. This ultrafast clock buffer is capable of
providing 1.9 V out of each side into a 50 Ω load terminated
to VCC (3.3 V) for a total differential swing of 3.8 V.
The buffer, in turn, can be easily driven from lower level signals
such as CML or attenuated PECL that might be encountered on
a PCB. This buffer also provides very low, 100 fs added random
jitter, which is important to obtain the optimal ac performance
from the AD9789. A functional block diagram of the ADCLK914
is shown in Figure 113. Figure 114 shows the recommended
schematic for the ADCLK914/AD9789 interface. Refer to the
ADCLK914 data sheet for more information. Any time that the
noise floor from the DAC cannot meet the specifications in this
data sheet, the clock should be examined.
V_CC
V_REF
V_T
ADCLK914
50Ω 50Ω
D
D
50Ω 50Ω
Q
Q
V_EE
Figure 113. ADCLK914 Functional Block Diagram
The internal 50 Ω resistors shown at the ADCLK914 inputs are
rated to carry currents from PECL or CML drivers. The VT pin
can be connected to VCC, a PECL current sink, or the internal
VREF, or it can be left floating depending on the source. The
common-mode input range of the ADCLK914 does not include
LVDS voltage levels, so ac coupling is required in that case.
J3
PSTRNKPE4117
1
C81
0.01µF
2 345
GND
C82
0.01µF
R15
49.9Ω
GND
GND
C83
0.01µF
VCC33
GND ^{16 15 14 13}
U3
ADCLK914
1D
2D
3 _NC
4 NC
Q ¹²
Q ¹¹
NC ¹⁰
NC 9
5 67 8
GND
VCC33
R13
49.9Ω
VCC33
R14
C99
49.9Ω ^2400pF
C0803H50
C102
2400pF
C0803H50
R17
100Ω
R0402
ADCLK914 SUPPLY DECOUPLING
VCC33
C31
0.1µF
C0402
C32
0.01µF
C0402
C33
0.1µF
C0402
C34
0.01µF
C0402
GND
GND
GND
GND
Figure 114. ADCLK914/AD9789 Interface Circuit for Use with a Lab Generator
CLKP
CLKN
Rev. A | Page 57 of 76