ADV7324 Datasheet, PDF (53/92 Pages) Analog Devices – Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs

ADV7324
PROGRAMMABLE DAC GAIN CONTROL
DAC A, DAC B, and DAC C are controlled by Register 0A.
DAC D, DAC E, and DAC F are controlled by Register 0B.
The I²C control registers will adjust the output signal gain up or
down from its absolute level.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESSES 0x0A, 0x0B
700mV
300mV
CASE B
700mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESSES 0x0A, 0x0B
300mV
Figure 69. Programmable DAC Gain—Positive and Negative Gain
In Case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.
In Case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal
is reduced from the reference signal.
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC tune feature can change this output
current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
The reset value of the vid_out_ctrl registers is 0x00; therefore,
nominal DAC current is output. Table 33 is an example of how
the output current of the DACs varies for a nominal 4.33 mA
output current.
Table 33. DAC Gain Control
Reg. 0x0A or
0x0B
DAC
Current
(mA)
0100 0000 (0x40) 4.658
0011 1111 (0x3F) 4.653
0011 1110 (0x3E) 4.648
...
...
...
...
0000 0010 (0x02) 4.43
0000 0001 (0x01) 4.38
0000 0000 (0x00) 4.33
% Gain
+7.5000%
+7.3820%
+7.3640%
...
...
+0.0360%
+0.0180%
+0.0000%
1111 1111 (0xFF)
1111 1110 (0xFE)
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
4.25
4.23
...
...
4.018
4.013
4.008
−0.0180%
−0.0360%
...
...
−7.3640%
−7.3820%
−7.5000%
Note
(I²C Reset Value,
Nominal)
GAMMA CORRECTION
[Subaddresses 0x24 to 0x37 for HD,
Subaddresses 0x66 to 0x79 for SD]
Gamma correction is available for SD and HD video. For each
standard, there are twenty 8-bit-wide registers. They are used to
program Gamma Correction Curve A and Gamma Correction
Curve B. HD Gamma Curve A is programmed at Address 0x24
to Address 0x2D, and HD Gamma Curve B is programmed at
Address 0x2E to Address 0x37. SD Gamma Curve A is
programmed at Address 0x66 to Address 0x6F, and SD Gamma
Curve B is programmed at Address 0x70 to Address 0x79.
Generally gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied
wherever nonlinear processing is used.
Gamma correction uses the function
Signal_OUT = (Signal_IN )^γ
where γ = gamma power factor.
Gamma correction is performed on the luma data only. The
user may choose either of two curves: Curve A or Curve B. At
any one time, only one of these curves can be used.
The response of the curve is programmed at 10 predefined
locations. By changing the values at these locations, the gamma
curve can be modified. Between these points, linear interpolation
is used to generate intermediate values. If the curve has a total
length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96,
128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed
and cannot be changed.
Rev. 0 | Page 53 of 92