ADV7324 Datasheet, PDF (32/92 Pages) Analog Devices – Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs

ADV7324
Table 15. Registers 0x3E to 0x43
SR7–
SR0
0x3E
Register
Bit Description
Reserved
Bit 7
0x3F
Reserved
0x40 SD Mode Register 0 SD Standard
SD Luma Filter
SD Chroma Filter
0
0
0
0
1
1
1
1
0x41
Reserved
0x42 SD Mode Register 1 SD PrPb SSAF
SD DAC Output 1
SD DAC Output 2
0x43 SD Mode Register 2
SD Pedestal
SD Square Pixel
SD VCR FF/RW Sync
SD Pixel Data Valid
SD SAV/EAV Step
0
Edge Control
1
SD Pedestal YPrPb
Output
SD Output Levels Y
SD Output Levels PrPb
SD VBI Open
SD CC Field Control
Reserved
0
Bit 6
0
0
1
1
0
0
1
1
0
1
0
0
1
1
Bit 5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit 4
0
0
0
0
1
1
1
1
0
1
0
1
Bit 3
0
0
1
1
0
0
1
1
0
1
0
0
1
1
Bit 2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit 1
0
0
1
1
0
1
0
1
Bit 0
0
1
0
1
0
1
0
1
Register Setting
NTSC.
PAL B, D, G, H, I.
PAL M.
PAL N.
LPF NTSC.
LPF PAL.
Notch NTSC.
Notch PAL.
SSAF luma.
Luma CIF.
Luma QCIF.
Reserved.
1.3 MHz.
0.65 MHz.
1.0 MHz.
2.0 MHz.
Reserved.
Chroma CIF.
Chroma QCIF.
3.0 MHz.
Disabled.
Enabled.
Refer to the Output
Configuration section.
Refer to the Output
Configuration section.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
No pedestal on YUV.
7.5 IRE pedestal on YUV.
Y = 700 mV/300 mV.
Y = 714 mV/286 mV.
700 mV p-p (PAL);
1000 mV p-p (NTSC).
700 mV p-p.
1000 mV p-p.
648 mV p-p.
Disabled.
Enabled.
CC disabled.
CC on odd field only.
CC on even field only.
CC on both fields.
Reserved.
Reset
Value
0x00
0x00
0x00
0x00
0x08
0x00
Rev. 0 | Page 32 of 92