ADUC836_02 Datasheet, PDF (52/80 Pages) Analog Devices – MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU

ADuC836
TIMERS/COUNTERS
The ADuC836 has three 16-bit Timer/Counters: Timer 0, Timer 1,
and Timer 2. The Timer/Counter hardware has been included
on-chip to relieve the processor core of the overhead inherent in
implementing timer/counter functionality in software. Each
Timer/Counter consists of two 8-bit registers: THx and TLx
(x = 0, 1, and 2). All three can be configured to operate either as
timers or event counters.
In Timer function, the TLx Register is incremented every machine
cycle. Thus it can be viewed as counting machine cycles. Since
a machine cycle consists of 12 core clock periods, the maximum
count rate is 1/12 of the core clock frequency.
In Counter function, the TLx Register is incremented by a 1-to-0
transition at its corresponding external input pin, T0, T1, or T2.
In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle
and a low in the next cycle, the count is incremented. The new
count value appears in the register during S3P1 of the cycle fol-
lowing the one in which the transition was detected. Since it takes
two machine cycles (16 core clock periods) to recognize a 1-to-0
transition, the maximum count rate is 1/16 of the core clock fre-
quency. There are no restrictions on the duty cycle of the external
input signal, but to ensure that a given level is sampled at least
once before it changes, it must be held for a minimum of one full
machine cycle. Remember that the core clock frequency is pro-
grammed via the CD0–2 selection bits in the PLLCON SFR.
User configuration and control of the timers is achieved via three
main SFRs: TMOD and TCON control the configuration of
Timers 0 and 1, while T2CON configures Timer 2.
TMOD
SFR Address
Power-On Default Value
Bit Addressable
Timer/Counter 0 and 1 Mode Register
89H
00H
No
Table XXVI. TMOD SFR Bit Designations
Bit Name Description
7
Gate
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while INT1 pin is high and TR1 control bit is set.
Cleared by software to enable Timer 1 whenever TR1 control bit is set.
6
C/T
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
5
M1
Timer 1 Mode Select Bit 1 (used with M0 Bit)
4
M0
Timer 1 Mode Select Bit 0.
M1 M0
0
0
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each
time it overflows.
1
1
Timer/Counter 1 stopped.
3
Gate
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while INT0 pin is high and TR0 control bit is set.
Cleared by software to enable Timer 0 whenever TR0 control bit is set.
2
C/T
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
1
M1
Timer 0 Mode Select Bit 1
0
M0
Timer 0 Mode Select Bit 0.
M1 M0
0
0
TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time
it overflows.
1
1
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit
timer only, controlled by Timer 1 control bits.
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