ADUC836_02 Datasheet, PDF (23/80 Pages) Analog Devices – MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU

PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC836 incorporates two independent ⌺-⌬ ADCs (primary
and auxiliary) with on-chip digital filtering intended for the mea-
surement of wide dynamic range, low frequency signals such as
those in weigh-scale, strain gage, pressure transducer, or tempera-
ture measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of eight input
ranges from ±20 mV to ±2.56 V being driven from one of three
differential input channel options AIN1/2, AIN3/4, or AIN3/2.
The input channel is internally buffered, allowing the part to
handle significant source impedances on the analog input and
ADuC836
allowing R/C filtering (for noise rejection or RFI reduction) to be
placed on the analog inputs if required. On-chip burnout currents
can also be turned on. These currents can be used to check that
a transducer on the selected channel is still operational before
attempting to take measurements.
The ADC employs a ⌺-⌬ conversion technique to realize up to
16 bits of no missing codes performance. The ⌺-⌬ modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc³ programmable
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at programmable
output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A
chopping scheme is also employed to minimize ADC offset errors.
A block diagram of the primary ADC is shown in Figure 7.
BURNOUT CURRENTS
TWO 100nA BURNOUT
CURRENTS ALLOW THE
USER TO EASILY DETECT
IF A TRANSDUCER HAS
BURNED OUT OR GONE
OPEN-CIRCUIT.
ANALOG INPUT CHOPPING
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE
CONVERSION CYCLE.
CHOPPING YIELDS
EXCELLENT ADC OFFSET
AND OFFSET DRIFT
PERFORMANCE.
PROGRAMMABLE GAIN
AMPLIFIER
THE PROGRAMMABLE
GAIN AMPLIFIER ALLOWS
EIGHT UNIPOLAR AND
EIGHT BIPOLAR INPUT
RANGES FROM 20mV TO
2.56V (EXT VREF = 2.5V).
DIFFERENTIAL
REFERENCE
THE EXTERNAL REFERENCE
INPUT TO THE ADuC836 IS
DIFFERENTIAL AND
FACILITATES RATIOMETRIC
OPERATION. THE EXTERNAL
REFERENCE VOLTAGE IS
SELECTED VIA THE XREF0 BIT
IN ADC0CON.
REFERENCE DETECT
CIRCUITRY TESTS FOR OPEN OR
SHORTED REFERENCE INPUTS.
REFIN(–) REFIN(+)
⌺-⌬ ADC
THE ⌺-⌬ ARCHITECTURE
ENSURES 24 BITS NO
MISSING CODES. THE
ENTIRE ⌺-⌬ ADC IS
CHOPPED TO REMOVE
DRIFT ERROR.
OUTPUT AVERAGE
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA-WORD OUTPUT
FROM THE FILTER IS
SUMMED AND AVERAGED
WITH ITS PREDECESSOR
TO NULL ADC CHANNEL
OFFSET ERRORS.
AIN1
AIN2
AIN3
AIN4
AV_DD
MUX
BUFFER
PGA
AGND
CHOP
⌺-⌬ ADC
⌺-⌬
MODULATOR
PROGRAMMABLE
DIGITAL
FILTER
CHOP
OUTPUT
AVERAGE
OUTPUT
SCALING
DIGTAL OUTPUT
RESULT WRITTEN
TO ADC0H/M/L
SFRS
ANALOG MULTIPLEXER
A DIFFERENTIAL MULTIPLEXER
ALLOWS SELECTION OF THREE
FULLY DIFFERENTIAL PAIR OPTIONS AND
ADDITIONAL INTERNAL SHORT OPTION
(AIN2–AIN2). THE MULTIPLEXER IS
CONTROLLED VIA THE CHANNEL
SELECTION BITS IN ADC0CON.
BUFFER AMPLIFIER
THE BUFFER AMPLIFIER
PRESENTS A HIGH
IMPEDANCE INPUT STAGE
FOR THE ANALOG INPUTS,
ALLOWING SIGNIFICANT
EXTERNAL SOURCE
IMPEDANCES.
⌺-⌬ MODULATOR
THE MODULATOR PROVIDES
A HIGH FREQUENCY 1-BIT
DATA STREAM (THE OUTPUT
OF WHICH IS ALSO CHOPPED)
TO THE DIGITAL FILTER,
THE DUTY CYCLE OF WHICH
REPRESENTS THE SAMPLED
ANALOG INPUT VOLTAGE.
PROGRAMMABLE
DIGITAL FILTER
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE
VIA THE SF SFR.
OUTPUT SCALING
THE OUPUT WORD FROM THE
DIGITAL FILTER IS SCALED
BY THE CALIBRATION
COEFFICIENTS BEFORE
BEING PROVIDED AS
THE CONVERSION RESULT.
Figure 7. Primary ADC Block Diagram
REV. 0
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