AD9522-3 Datasheet, PDF (52/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO

AD9522-3
Data Transfer Format
Send byte format—the send byte protocol is used to set up the register address for subsequent commands.
S Slave Address
W A RAM Address High Byte
A RAM Address Low Byte
AP
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
RAM Address
RAM Address
S Slave Address W A High Byte
A Low Byte
A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S Slave Address
R A RAM Data 0
A RAM Data 1
A RAM Data 2
AP
Read byte format—the combined format of the send byte and the receive byte.
Slave
RAM Address
RAM Address
Slave
RAM
RAM
RAM
S Address W A High Byte
A Low Byte
A Sr Address R A Data 0 A Data 1 A Data 2 A P
I²C Serial Port Timing
SDA
t_FALL
SCL
S
t_LOW
t_{SET; DAT}
t_RISE
t_FALL
t_{HLD; STR}
t_{HLD; STR}
t_{HLD; DAT}
t_HIGH
t_{SET; STR}
Sr
Figure 61. I²C Serial Port Timing
t_SPIKE
t_RISE
t_IDLE
t_{SET; STP}
P
S
Table 41. I2C Timing Definitions
Parameter
Description
fI2C
I²C clock frequency
tIDLE
Bus idle time between stop and start conditions
tHLD; STR
Hold time for repeated start condition
tSET; STR
Setup time for repeated start condition
tSET; STP
Setup time for stop condition
tHLD; DAT
Hold time for data
tSET; DAT
Setup time for data
tLOW
Duration of SCL clock low
tHIGH
Duration of SCL clock high
tRISE
SCL/SDA rise time
tFALL
SCL/SDA fall time
tSPIKE
Voltage spike pulse width that must be suppressed by the input filter
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