ADV7340_15 Datasheet, PDF (51/108 Pages) Analog Devices – Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS

Data Sheet
ENHANCED DEFINITION/HIGH DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 001 or 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in either 4:2:2 or 4:4:4 format. If desired, dual data
rate (DDR) pixel data inputs can be employed (4:2:2 format only).
Enhanced definition (ED) or high definition (HD) RGB data
can be input in 4:4:4 format (single data rate only).
The clock signal must be provided on the CLKIN_A pin. Input
synchronization signals are provided on the P_HSYNC,
P_VSYNC, and P_BLANK pins.
16-/20-Bit 4:2:2 YCrCb Mode (SDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
In 16-/20-bit 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin Y9 to Pin Y2/Y0, with Pin Y0 being the LSB in
20-bit input mode.
The CrCb pixel data is input on Pin C9 to Pin C2/C0, with Pin C0
being the LSB in 20-bit input mode.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin Y9 to Pin Y2/Y0 on either the rising or falling edge
of CLKIN_A. Pin Y0 is the LSB in 10-bit input mode.
The CrCb pixel data is also input on Pin Y9 to Pin Y2/Y0 on the
opposite edge of CLKIN_A. Pin Y0 is the LSB in 10-bit input
mode.
Whether the Y data is clocked in on the rising or falling edge
of CLKIN_A is determined by Subaddress 0x01, Bits[2:1] (see
Figure 52 and Figure 53).
CLKIN_A
Y[9:0]
3FF 00
00
XY Cb0 Y0 Cr0 Y1
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
CLKIN_A
Y[9:0]
3FF 00
00
XY
Y0 Cb0 Y1
Cr0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
24-/30-Bit 4:4:4 YCrCb Mode
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0
In 24-/30-bit 4:4:4 YCrCb input mode, the Y pixel data is input on
Pin Y9 to Pin Y2/Y0, with Pin Y0 being the LSB in 30-bit input
mode.
ADV7340/ADV7341
The Cr pixel data is input on Pin S9 to Pin S2/S0, with Pin S0
being the LSB in 30-bit input mode. The Cb pixel data is input
on Pin C9 to Pin C2/C0 (Pin C0 being the LSB in 30-bit input
mode).
24-/30-Bit 4:4:4 RGB Mode
Subaddress 0x35, Bit 1 = 1
In 24-/30-bit 4:4:4 RGB input mode, the red pixel data is input
on Pin S9 to Pin S2/S0, the green pixel data is input on Pin Y9
to Pin Y2/Y0, and the blue pixel data is input on Pin C9 to
Pin C2/C0. The S0, Y0, and C0 pins are the respective bus LSBs
in 30-bit input mode.
MPEG2
DECODER
YCrCb
INTERLACED TO
PROGRESSIVE
Cb ¹⁰
Cr ¹⁰
Y ¹⁰
ADV7340/
ADV7341
CLKIN_A
C[9:0]
S[9:0]
Y[9:0]
3
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 54. ED/HD Only Example Application
SIMULTANEOUS STANDARD DEFINITION AND
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 011 or 100
The ADV7340/ADV7341 are able to simultaneously process
SD 4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27
MHz SD clock signal must be provided on the CLKIN_A pin.
The ED/HD clock signal must be provided on the CLKIN_B
pin. SD input synchronization signals are provided on the
S_HSYNC and S_VSYNC pins. ED/HD input synchronization
signals are provided on the P_HSYNC, P_VSYNC, and
P_BLANK pins.
SD 8-/10-Bit 4:2:2 YCrCb and ED/HD-SDR 16-/20-Bit
4:2:2 YCrCb
The SD 8-/10-bit 4:2:2 YCrCb pixel data is input on Pin S9 to
Pin S2/S0, with Pin S0 being the LSB in 10-bit input mode.
The ED/HD 16-/20-bit 4:2:2 Y pixel data is input on Pin Y9 to
Pin Y2/Y0, with Pin Y0 being the LSB in 20-bit input mode.
The ED/HD 16-/20-bit 4:2:2 CrCb pixel data is input on Pin C9
to Pin C2/C0, with Pin C0 being the LSB in 20-bit input mode.
SD 8-/10-Bit 4:2:2 YCrCb and ED/HD-DDR 8-/10-Bit
4:2:2 YCrCb
The SD 8-/10-bit 4:2:2 YCrCb pixel data is input on Pin S9 to
Pin S2/S0, with Pin S0 being the LSB in 10-bit input mode.
The ED/HD-DDR 8-/10-bit 4:2:2 Y pixel data is input on Pin Y9
to Pin Y2/Y0 upon the rising or falling edge of CLKIN_B. Pin Y0
is the LSB in 10-bit input mode.
Rev. C | Page 51 of 108