ADV7342_15 Datasheet, PDF (50/108 Pages) Analog Devices – Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs

ADV7342/ADV7343
Whether the ED/HD Y data is clocked in on the rising or falling
edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1]
(see the input sequence shown in Figure 52 and Figure 53).
SD
DECODER
2
27MHz
YCrCb ⁸
HD
DECODER
525p
OR
625p
CrCb ⁸
Y8
3
74.25MHz
S_VSYNC,
S_HSYNC
CLKIN_A
S[7:0]
ADV7342/
ADV7343
C[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
Figure 55. Simultaneous SD and ED Example Application
2
SD
DECODER
27MHz
YCrCb ⁸
HD
DECODER
CrCb
8
1080i
OR _Y
8
720p
OR
3
1035i
74.25MHz
S_VSYNC,
S_HSYNC
CLKIN_A
S[7:0]
ADV7342/
ADV7343
C[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
Figure 56. Simultaneous SD and HD Example Application
Data Sheet
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the P_HSYNC,
P_VSYNC, and P_BLANK pins.
The interleaved pixel data is input on Pin Y7 to Pin Y0, with
Pin Y0 being the LSB.
CLKIN_A
Y[7:0]
3FF 00
00
XY Cb0 Y0 Cr0 Y1
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECODER
YCrCb
54MHz
YCrCb ⁸
INTERLACED TO
PROGRESSIVE
3
CLKIN_A
ADV7342/
ADV7343
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 58. ED Only (at 54 MHz) Example Application
Rev.D | Page 50 of 108