ADV7342_15 Datasheet, PDF (18/108 Pages) Analog Devices – Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs

ADV7342/ADV7343
Data Sheet
Y OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y7 TO Y0
C7 TO C0
c
a
Y0 Y1 Y2 Y3
Cb0 Cr0 Cb2 Cr2
b
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 16. HD-SDR, 16-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Cb0 Y0 Cr0 Y1
b
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev.D | Page 18 of 108